Broadcom Corporation

James Douglas Sweet

Thu T Nguyen

Darren Duane Neuman

Steven T Jaffe

Brian Francis Schoner

Rajesh Mamidwar

Chengfuh Jeffrey Tang

Greg Alan Kranawetter

Patrick Y Law

Iue-Shuenn Chen

Sandeep Bhatia

Aleksandr M Movshovich

Jason C Demas

Francis Cheung

Brad Albert Delanghe

David A Baer

Hoang Nhu

Ut Nguyen

Tracy C Denk

Shawn Val Johnson

Yao-Hua Tseng

Guang-Ting Shih

Jeffrey S Bauch

Brad Grossman

David Chao Hua Wu

Chuck Monahan

Dan Simon

Sang Van Tran

Hsien-Chih Jim Tseng

Ben Giese

Lakshman Ramakrishnan

Jeff Tingley

Keith LaRell Klingler

Amar Guettaf

Keith LaRell Klinger

Tianwen Tang

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Television functionality on a chip

Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.

Method and system of using a single EJTAG interface for multiple tap controllers

A system (e.g., a chip) includes first and second function blocks (e.g., function blocks) coupled to an input/output (I/O) device (e.g., a bi-directional pin or pad) via a multiplexing module. The multiplexing module can be used for both input and output of signals between the function blocks and the I/O device. Optionally, a re-clocking system is coupled to the function blocks, the I/O device, and the multiplexing module. The re-clocking system re-clocks one or more signals being input into the multiplexing module so that they are timed correctly for input or output from the system.

System and method using an I/O multiplexer module

A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

System and method having strapping with override functions

Methods and systems for synchronizing a reset signal with a local clock that drives a circuit. In the circuit, the reset signal can be used to reset one or more flip-flops, memory devices, and/or logic. Sychronization of the reset signal allows the reset signal to change at an appropriate time period in relation to the lock clock signal driving the circuit. This ensures the circuit will remain stable during reset, and no data will be lost as it is processed in the circuit. Other aspects of the invention can include using a plurality of reset signals (e.g., software, hardware, local software, etc.) to form the reset signal and using a reset control system to control resets during testing of the circuit.

Systems for synchronizing resets in multi-clock frequency applications

Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.

Method and system for ensuring the assertion order of signals in a chip independent of physical layout

A method and apparatus are disclosed for easily reconfiguring a scan chain test of a subset of scan blocks within a digital integrated circuit chip. To mitigate timing violations in the scan test of scan chains, alternative embodiments to implement a transfer of scan data to a next scan block are implemented.

Methodology for selectively testing portions of an integrated circuit

One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a display. In one embodiment, the method includes executing a set of instructions operating on a register design parameter file to produce an output that is easily incorporated into the integrated circuit design simulator software. The output specifies one or more tests to be performed using the integrated circuit design simulator software. The one or more tests are subsequently performed to validate the register design. The method automates the incorporation of register design parameters into the integrated circuit design simulator software by way of executing a set of instructions that operates on the register design parameter file.

Testing of integrated circuits from design documentation

Growing community of inventors

Sunnyvale, CA, United States of America

James Douglas Sweet