Motorola Corporation

Other

Certicom Corporation

Freescale Semiconductor,inc.

James Douglas Dworkin

Michael J Torla

John Michael Buss

Scott Alexander Vanstone

Stephen L Smith

Ashok Vadekar

Robert John Lambert

Rodney C Tesch

P Michael Glaser

Shay-Ping T Wang

Scott Edward Lloyd

Robert I Foster

Philip B Giangarra

Shao Wei Pan

ShaoWei Wei Pan

A Message Digest Hardware Accelerator (MDHA)for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file () is initialized to different data values. A function circuit () performs logical operations based on the selected algorithm and provides a data value to a summing circuit () that is summed with mode dependent constant values selected from registers (and), round and step dependent data words generated by a register array block () to calculate the hash value for a text message stored in registers ().

Circuit for generating hash values

A co-processor ( ) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier ( ) receives sixteen bit data values stored in an A/B RAM ( ) and generates a partial product. The generated partial product is summed in an adder ( ) with a previous partial product stored in a product RAM ( ). A modulo reducer ( ) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM ( ) stores the data value N that is added in a modulo reducer ( ) to the summed value. The co-processor ( ) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method for fast modular multiplication

A system for efficiently controlling the exchange of data between a host bus (,) and an input/output (I/O) register (,) of an elliptic curve (EC) processor (,) having a much wider datapath than that of the host device (,) . A spreading/despreading pattern is determined which spans multiple bit positions of the input/output register (,). In one embodiment, a full combinational circuit (,) is provided to connect a bit position of the host bus (,) to a bit position of the input/output register (,). In another embodiment, a combinational circuit (,) and an intermediate register (,) are provided. In still another embodiment, a spreading-by shifting system (,) is provided which comprises a plurality of subfield modules (,) into which data from the host bus (,) is shifted. The spreading/despreading pattern is achieved through multiplexers (,) connected between the subfield modules (,). In yet another embodiment, a cross bar switch (,) is provided to connect any bit position of the host bus (,) to any bit position of the I/O register,. In each embodiment, an EC control unit (,) is provided which stores information for the spreading/despreading pattern.

System for controlling data exchange between a host device and a processor

A programmable versatile digital signal processing system architecture (FIG.,) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG.,) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS.,and,).

Versatile digital signal processing system

A finite field multiplier with intrinsic modular reduction includes an interface unit (,) that translates an n bit wide data path to a m bit wide data path where n is less than m. Also included is a finite field data unit (,) with m bit wide registers that is coupled to a finte field control unit (,). The finite field control unit (,) includes a microsequencer (,) and a finite state machine multiplier (,). The microsequencer (,) controls the finite state machine multiplier (,) which performs a finite field multiply operation with intrinsic modular reduction and presents a finite field multiplication product to the finite field data unit (,).

Finite field multiplier with intrinsic modular reduction

An elliptic curve (EC) processor circuit (,) comprising a finite field arithmetic logic unit (,), operation registers (,) an EC control unit (,) and a register file (,). A storage element (,) is coupled to the finite field arithmetic logic unit (,). The EC control unit (,) controls the various components of the EC processor circuit (,) to decompress a compressed one-bit representation of a Y coordinate of an elliptic curve point (X, Y). The EC control unit (,) controls the use of the operation register (,), the storage element (,) and the finite field arithmetic logic unit (,) to recursively compute the decompressed version of the compressed Y coordinate based upon the X coordinate and the compressed one-bit representation of the Y coordinate. The circuit and method employ minimal additional hardware and processing in an EC processor circuit (,).

Circuit and method for decompressing compressed elliptic curve points

A co-processor (,) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (,) receives sixteen bit data values stored in an A/B RAM (,) and generates a partial product. The generated partial product is summed in a summer (,) with a previous partial product stored in a product RAM (,). A modulo reducer (,) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (,) stores the data value N that is added in a modulo reducer (,) to the summed value. The co-processor (,) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method of modulo multiplication

A programmable numeric converter (10) converts a floating point number to a fixed point format by selecting the proper offset. The mantissa is loaded with an implied value one into the least significant, or most significant, bits of the shifter (20). The programmable offset is added (24) to the exponent to determine the number of shifts to the mantissa bits. The number of bits of resolution necessary in the fixed point number is reduced because the offset can be programmed to move the decimal point to the left, or to the right, to provide accuracy wherever the significant digits are located. That is, the decimal point is moved left to provide more resolution in the fractional portion of the fixed point number for small numbers. Alternately, the decimal point is moved right to provide more resolution in the whole number portion of the fixed point number for large numbers.

Circuit and method of converting a floating point number to a

A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a k.sub.l and k.sub.u decrementer pair (1108, 1122), a k.sub.l -k.sub.u difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single '1' is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.

Finite field inverse circuit

A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

Galois field arithmetic logic unit circuit

A finite field inverse circuit (600) for use in an elliptic curve processor (12). The finite field inverse circuit (600) comprises a control circuit (610) and a data circuit (660). The data circuit (610) comprises a data multiplexer (668) for coupling the contents of one of three registers (662, 664, 680) to a finite field arithmetic logic unit (122). A first plurality of bits representing the finite field element to be inverted is initially loaded into a first one of the three registers. The control circuit (660) comprises a shift register (614) suitable for storing a second plurality of bits representing a size of the finite field element to be inverted. Counter and detection circuitry (630) is provided and coupled to the shift register (614) to decrement, shift and detect contents of the shift register (614) that generates control signals (CS1, CS2 and CS3) connected to the control signal inputs (C1, C2 and C3) of the multiplexer (668) of the data circuit (660) in order to cause a series of finite field operations to be performed upon the contents of the three registers (662, 664 and 680) to compute an inverse of the first plurality of bits representing the finite field element.

Finite field inverse circuit for use in an elliptic curve processor

A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).

Hybrid instruction set for versatile digital signal processing system

A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

Exponentiation circuit utilizing shift means and method of using same

A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable, The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript, The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

Computational array and method for calculating multiple terms of a

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

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Chandler, AZ, United States of America

James Douglas Dworkin