Arm Limited

Mediatek Corporation

James Dennis Dodrill

Yew Keong Chong

Satheesh Balasubramanian

Shardendu Shekhar

Andy Wangkun Chen

Marlin Wayne Frederick, Jr

Karen Lee Delk

Anil Kumar Baratam

Amanda Ashley Scantlin

Lena Ahlen

Sainarayanan Karatholuvu Suryanarayanan

George McNeil Lattimore

Michael J Allen

Mudit Bhargava

Gus Wai-Yan Yeung

Sriram Thyagarajan

Joel Thornton Irby

Wendy Arnott Elsasser

Joern Soerensen

Paul Christopher De Dood

Joseph Patrick Geisler

Ramesh Manohar

Susan Marie Graham

Lars Soendergaard Bertelsen

Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.

Modular gated multiplier circuitry and multiplication technique

A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

Non-volatile memory on chip

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Critical path architect

Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.

Sequential logic device with single-phase clock operation

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Location-based optimization for memory systems

A circuit to sample an input signal in an asynchronous clock domain. The apparatus includes a first latch configured to favor resolving to a logical high level and a second latch configured to favor resolving to a logical low level. The circuit includes a pullup pMOSFET, and first and second pMOSFETs. The first pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to a first input port of the first latch, and a drain terminal coupled to a second output port of the second latch. The second pMOSFET has a source terminal coupled to the drain terminal of the pullup pMOSFET, a gate coupled to the second output port of the second latch, and a drain terminal coupled to the first input port of the first latch.

Apparatus and method for reduced latency signal synchronization

A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Method and apparatus for adjusting a timing derate for static timing analysis

An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.

A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

Method for adjusting a timing derate for static timing analysis

A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained. Such an approach provides a particularly simple and efficient mechanism for deriving timing information for various circuit blocks that include a storage element.

Measurements circuitry and method for generating an oscillating output signal used to derive timing information

A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Synchroniser flip-flop

An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.

Growing community of inventors

Dripping Springs, TX, United States of America

James Dennis Dodrill