Actel Corporation, Inc.

Ramtron International Corporation

Enhanced Memory Systems, Inc.

Other

James Dean Joseph

William C Plants

Arunangshu Kundu

Wayne W Wong

Nikhil Mazumder

Dion Nickolas Heisler

Doyle James Heisler

Antony G Bell

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Delay locked loop for an FPGA architecture

Delay locked loop for and FPGA architecture

A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

Embedded static random access memory for field programmable gate array

The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache. The allocation unit accepts as input hit or miss information from page segment comparators greater than or equal to in number the number of segments of cache.

EDRAM having a dynamically-sized cache memory and associated method

A computer system with a hybrid main memory which includes both EDRAM and DRAM, with a DRAM cache provided within a designated portion of the EDRAM portion of the main memory. Read requests are handled by copying data being read from DRAM into a cache portion of EDRAM under the direction of a pseudo cache controller and decoder which converts the DRAM address to a EDRAM address corresponding to the cache location of EDRAM. Read 'hit' requests are responded to by reading data directly from the cache portion of EDRAM. Write requests to DRAM are, for purposes of cache coherency when a copy of the address being written to is present in the EDRAM cache portion, accomplished by writing data both to DRAM and overwriting the stale data existing in the cache portion of EDRAM.

Computer hybrid memory including DRAM and EDRAM memory components, with

An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.

EDRAM with integrated generation and control of write enable and column

A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

Multibus cached memory system

A single address register control technique for a memory controller allows both cache 'reads' and page-mode 'writes' to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.

Growing community of inventors

Monument, CO, United States of America

James Dean Joseph