Synopsys, Inc.

Groq, Inc.

Kawa, Jamil

Moroz, Victor

Sproch, James D.

Lefferts, Robert B.

James David Sproch

Victor Moroz

Jamil Kawa

Janet L Olson

Ivailo Nedelchev

Ashutosh S Mauskar

Xiaopeng Xu

Yueqin Danny Lin

Aditya Pradeep Karmarkar

Dinesh Maheshwari

Qing Su

Robert Beverly Lefferts

Zongwu Tang

Min Ni

Renu Mehra

John Pasternak

Brian Lee Kurtz

Michael M&uuml;nch

Bernd Wurth

Michael Munch

Yuegin Danny Lin

Luca Benini

Robert B Lefferts

Clock period synthesis for fine-grain power management is provided. Methods are described for enabling clock waveform synthesis for, in some embodiments, tensor or graphical processors that enable shorter runtime latency, higher computational job throughput, more efficient power management, and a lower implementation cost than alternative clock waveform methods. This Abstract and the independent Claims are concise signifiers of embodiments of the claimed inventions. The Abstract does not limit the scope of the claimed inventions.

Generation of clock waveforms based on decoded instructions for more efficient power management in high-speed processors

One or more embodiments of a regulator circuit for providing power to a load device having a first power demand profile over time. The regulator circuit comprises a regulator and an energy storage device coupled to the regulator and the load device. The regulator circuit is configured to scavenge provided energy that is available beyond the first power demand profile. Further, the regulator circuit is configured to store that energy in the energy storage device, and the energy storage device is configured to augment deliverable peak power to the load device when the load device requires more power than is provided by the regulator circuit.

Energy provisioning

A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions. The processed instructions are dispatched to columns of the computational array via a plurality of instruction queues, wherein an instruction vector of instructions is shifted between adjacent instruction queues in a first direction, and dispatches instructions to the computational elements in a second direction.

Processor instruction dispatch configuration

In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Method and apparatus for floating or applying voltage to a well of an integrated circuit

Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Placing transistors in proximity to through-silicon vias

Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

ESD/antenna diodes for through-silicon vias

A latch is analyzed to determine meta-stable voltage bias points, which are then used to determine one or more of a settling time of the latch, a mean time before failure (MTBF) for a synchronizing circuit using the latch, or a regeneration time constant (Tau). The latch is analyzed by decomposing the latch circuit into a feed-forward circuit and a feedback circuit and then determining a first transfer function for the feed-forward circuit and a second transfer function for the feedback circuit. The transfer functions are then used to solve for meta-stable voltage bias points. The meta-stable voltage bias points are used as an initial condition for a simulation or measurement of the latch in order to measure settling time. The voltage curve during the settling time of the latch is used to calculate a value for Tau.

Determination of meta-stable latch bias voltages

Method and apparatus for placing transistors in proximity to through-silicon vias

Growing community of inventors

Monte Sereno, CA, United States of America

James David Sproch