Nvidia Corporation

James David Balfour

Brucek Kurdo Khailany

Ronny Krashinsky

William James Dally

Ignacio Llamas

Ignacio Llamas Ubieto

A first thread is placed into a blocked state by causing the thread to perform a blocking pop operation on a hardware-accelerated, single-entry queue. When a synchronization event completes, a second thread may release the first thread from the blocked state pushing a data value onto the hardware accelerated, single-entry queue. The push operation satisfies the blocking pop operation, and the first thread is released.

Low overhead thread synchronization using hardware-accelerated bounded circular queues

A system, method, and computer program product are provided for accessing a queue. The method includes receiving a first request to reserve a data record entry in a queue, updating a queue state block based on the first request, and returning a response to the request. A second request is received to commit the data record entry and the queue state block is updated based on the second request.

System, method, and computer program product for a two-phase queue

A system, method, and computer program product are provided for managing miss requests. In use, a miss request is received at a unified miss handler from one of a plurality of distributed local caches. Additionally, the miss request is managed, utilizing the unified miss handler.

System, method, and computer program product for managing cache miss requests

A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (SRAM). Additionally, the storage array is utilized in a multithreaded architecture.

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Mountain View, CA, United States of America

James David Balfour