Agere Systems Inc.

Agere Systems Guardian Corp.

James D Yoder

Johannes Gerardus Ransijn

Peter Kiss

Boris A Bark

Harold Simmonds

Brad L Grande

Jesus Arias

King-Hon Lau

Dwight David Daugherty

John Wayne Bowen

Roger Anthony Fratti

Gregory C Salvador

Kenneth D Gaynor

The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.

Signal-powered integrated circuit with ESD protection

The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the &#x3a3;&#x394; rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.

Serial protocol for agile sample rate switching

The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

Continuous power transfer scheme for two-wire serial link

Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.

Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters

Single-transformer digital isolation barrier

An electro-optic modulator and associated method are provided. The electro-optic modulator includes an optical waveguide comprised of two pairs of coplanar modulation strips, the strips being driven by a controller circuit which applies voltages of equal amplitude and opposite polarity to the strips of each pair. The voltage applied to the first pair of strips may differ from the voltage applied to the second pair of strips, so that a chirp factor may be adjusted if desired. The modulator and associated method exhibit reduced drive voltage requirements.

LiNbO3 Mach-Zehnder modulator with low drive voltage requirement and adjustable chirp

A system and method are provided for providing an impedance match of an output buffer to a transmission line without significantly increasing the power consumption of the output buffer. A system and method are also provided for providing an impedance match of an output buffer to a transmission line, while still allowing for an adjustable output swing as is required for loads such as laser transmitters and optical modulators.

System and method for providing an impedance match of an output buffer to a transmission line

There is disclosed a power amplifier includes an in-phase power splitter generating two split signals from an input signal, and two amplifiers capable of operating in different modes. The split signals are provided as respective inputs to the two amplifiers which are coupled through transmission lines such that as the first amplifier approaches the maximum power it can produce, the output from the second amplifier begins to contribute to the power amplifier output and supplements and modifies the power provided by the first amplifier thereby extending the range of input power over which the power amplifier delivers output power.

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Leola, PA, United States of America

James D Yoder