Freescale Semiconductor,inc.

Freescale Semiconductors Inc.

Nxp Usa, Inc.

James D Whitfield

Chai Ean Gill

Rouying Zhan

Hongzhong Xu

Changsoo Hong

Abhijat Goyal

Richard T Ida

Chai Ean E Gill

Michael Baird

Sopan Joshi

Jinman Yang

Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.

Devices with zener triggered ESD protection

An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb'. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb&#x2032;. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vtis low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vtrises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Multi-voltage electrostatic discharge protection

An electrostatic discharge (ESD) clamp (), coupled across input-output (I/O) () and common (GND) () terminals of a protected semiconductor SC device or IC (), comprises, an ESD transistor (ESDT) () with source-drain () coupled between the GND () and I/O (), a first resistor () coupled between gate () and source () and a second resistor () coupled between ESDT body () and source (). Paralleling the resistors () are control transistors () with gates () coupled to one or more bias supplies Vb, Vb'. The main power rail (Vdd) of the device or IC () is a convenient source for Vb, Vb&#x2032;. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vtis low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vtrises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT () during normal operation is much reduced.

Electrostatic discharge (ESD) protection clamps () for I/O terminals () of integrated circuit (IC) cores () comprise a bipolar transistor () with an integrated Zener diode () coupled between the base () and collector () of the transistor (). Prior art variations () in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants () and forming the base () coupled anode () and collector () coupled cathode () of the Zener () using opposed edges () of a single relatively thin mask (). The anode () and cathode () are self-aligned and the width () of the Zener space charge region () therebetween is defined by the opposed edges () substantially independent of location and orientation of the ESD clamps () on the die or wafer. Because the mask () is relatively thin and the anode () and cathode () implants () relatively shallow, mask shadowing is negligible and prior art clamp voltage variations () are avoided.

Zener triggered ESD protection

An electrostatic discharge (ESD) protection device () coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (&#x2033;), each stage (&#x2033;) comprising first (T, T', T&#x2033;, etc.) and second transistors (T, T&#x2032;, T&#x2032;&#x2033; etc.) having a common collector (&#x2033;) and first (&#x2033;) and second (&#x2033;) emitters providing terminals (&#x2033;) of each clamp stage (. A first emitter () of the first stage () couples to the common terminal () and a second emitter (&#x2033;) of the last stage (&#x2032;) couples to the I/O terminals (). Zener diode triggers are not used. Integrated external ESD trigger resistors (&#x2033;) (e.g., of poly SC) are coupled between the base (&#x2033;) and emitter (&#x2033;) of each transistor (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;). Different resistor values (e.g., &#x2dc;0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages () gives even higher trigger voltages. The ESD trigger resistances (&#x2033;) are desirably located outside the common collector-isolation wall (&#x2033;) surrounding the transistors (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;).

Resistor triggered electrostatic discharge protection

An improved lateral bipolar electrostatic discharge (ESD) protection device () comprises a semiconductor (SC) substrate (), an overlying epitaxial SC layer (), emitter-collector regions () laterally spaced apart by a first distance () in the SC layer, a base region () adjacent the emitter region () extending laterally toward and separated from the collector region () by a base-collector spacing () that is selected to set the desired trigger voltage Vt. By providing a buried layer region () under the emitter region () Ohmically coupled thereto, but not providing a comparable buried layer region () under the collector region (), an asymmetrical structure is obtained in which the DC trigger voltage (Vt) and transient trigger voltage (Vt) are closely matched so that |Vt&#x2212;Vt|&#x2dc;0. This close matching increases the design margin and provides a higher performance ESD device () that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

Buried asymmetric junction ESD protection device

An electrostatic discharge (ESD) protection clamp () for I/O terminals () of integrated circuits (ICs) () comprises an NPN bipolar transistor () coupled to an integrated Zener diode (). Variations in the break-down current-voltage characteristics () of multiple prior art ESD clamps () in different parts of the same IC chip is avoided by forming the anode () of the Zener () in the shape of a base-coupled P+ annular ring () surrounded by a spaced-apart N+ annular collector ring () for the cathode () of the Zener (). Even though an angled implant () used to form the N+ annular collector ring () causes location dependent variations in the width () of the Zener space charge (ZSC) region (), the improved annular shaped clamp () always has a portion that initiates break-down at the design voltage so that variations in the width () of the ZSC region () do not cause significant variations in the clamp's current-voltage characteristics ().

Complementary zener triggered bipolar ESD protection

An electrostatic discharge (ESD) protection device (), coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (), each stage () comprising an interior node () and first () and second terminal () nodes wherein the first terminal node () of the first clamp stage () is coupled to the common terminal () and the second terminal node () of the last clamp stages () is coupled to the I/O terminals (). A resistance-capacitance ladder () is provided in parallel with some of the clamp stages (), with a resistance (R, R, Retc.) coupled to each of the nodes (()) of one of the ESD clamp stages () by first terminals thereof and capacitors (C, C, etc.) are coupled between second terminals of the resistances (R, R, Retc.). The clamp stages () are desirably bi-directional and a diode (D) may bridge one or more of the clamp stages (e.g.,) to provide different clamp voltages for different polarity ESD events.

Electrostatic discharge protection

Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Low voltage NMOS-based electrostatic discharge clamp

An ESD protection device () comprises an N-type epitaxial collector (), a first, lightly doped, deep base region () and second, highly doped, shallow base region () that extends a predetermined lateral dimension. The device responds to an ESD event by effecting vertical breakdown between the base regions and the N-type epitaxial collector. The ESD response is controlled by the predetermined lateral dimension, S, which, in one embodiment, may be is determined by a single masking step. Consequently, operation of the ESD protection device is rendered relatively insensitive to the tolerances of a fabrication process, and to variations between processes.

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Gilbert, AZ, United States of America

James D Whitfield