Advanced Micro Devices Corporation

International Business Machines Corporation

James D Werking

Theodorus E Standaert

Andrew Herbert Simon

Ronald G Filippi

Kaushik Chanda

Stephan Grunow

Matthias Schaller

Mario M Pelella

Paul Stephen McLaughlin

Richard K Klein

Sujatha Sankaran

Tibor Bolom

Massud Abubaker Aminpur

A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.

Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing

A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.

Method for fabricating an SOI device

By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.

Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics

A scribe seal ( ) and a method for manufacturing the scribe seal ( ) and a semiconductor component including the scribe seal ( ). A semiconductor substrate ( ) has a major surface ( ) and a crack arrest structure ( ) formed on the major surface ( ). A dielectric material ( ) is formed on a portion of the semiconductor substrate ( ) adjacent the crack arrest structure ( ). A nitride layer ( ) is formed on the crack arrest structure ( ) and the dielectric material ( ). An oxide layer ( ) is formed on the nitride layer ( ). An opening ( ) is formed in the oxide layer ( ) and the nitride layer ( ) and lands on and exposes a portion of the dielectric material ( ). A crack arrest material such as, for example, copper, is formed in the opening ( ). A semiconductor device is formed in the semiconductor substrate ( ).

Scribe seal structure and method of manufacture

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Austin, TX, United States of America

James D Werking