Intel Corporation

James D Warren

Brian J Skerry

Sailesh Bissessur

Richard Paul Mackey

Stephen M Sacker

Ralph Gundacker

Richard P Luckett

George R Munce

In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to the indication, a signal may be provided that may result in the coupling of a signal line of a second device to the bus. After the provision of the signal, the first device may configure the second device. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Device configuration

A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Power loss memory back-up

An input/output device on a bus may be controlled to enable advanced features such as RAID to be implemented on a system board which is not otherwise specially adapted in any fashion to implement such features. The system board need not include, in its basic configuration, a host bus adapter such as one using an I/O processor, or standard BIOS instructions which assist in the implementation of the advanced features. The advanced features may be implemented by plugging an appropriate host bus adapter into an appropriate bus slot to provide the advanced functionality. By using special logic and signals on the host bus adapter, the advanced functionality may be achieved in a platform independent system board implementation and without the added cost of an I/O device on the host bus adapter.

Controlling I/O devices independently of a host processor

A cache SRAM connector assembly comprising a connector, a number of latches, and a number of high performance switches, is provided to a computer system. The connector removably connects either asynchronous or burst cache SRAM to a processor bus. The latches store cache access addresses being driven on a number of address lines of the processor bus. The high performance switches being coupled to both the latches and the address lines of the processor bus selectively provide the cache SRAM with latched access addresses as required by asynchronous cache SRAM or directly driven access addresses on the processor bus as required by burst cache SRAM.

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Gilbert, AZ, United States of America

James D Warren