International Business Machines Corporation

James D Wagoner

Hector G Romero, Jr

Joe C St Clair

Paul William Coteus

Warren Edward Maule

Leon Lumelsky

Alphonso Philip Lanzetta

Stephen Douglas Weitzel

Gilles Gervais

Marc Segre

Alexander K Spencer

John W Irwin

Robert L Mansfield

Satish Gupta

James M McVey

Daniel J Phipps

James K Tam

Ralph Herman Genz

A memory clock generator apparatus and method are implemented. The memory clock is generated, &ldquo;open loop,&rdquo; from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.

Memory clock generator and method therefor

A data processing system including an improved method and apparatus for the arrangement and interconnection between electronic devices to improve system cycle time. The apparatus possesses a) a plurality of: memory SIMMs, memory devices on the noted memory SIMMs and registers; b) a clock; c) means for connecting signals between the memory devices on the memory SIMMs and the registers; and d) means for connecting signals between the memory devices on the memory SIMMs and the clocks.

Clustered, buffered simms and assemblies thereof

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

High resolution graphics display adapter

In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.

Serial link transparent mode disparity control

A counter is used to concurrently refresh a video display and a memory associated with such video display. Address bits are output from the counter to the sync decode logic used to refresh the display as well as to multiplexing means connected to the associated memory. The multiplexing means has three pairs of inputs. The first pair of inputs comprises refresh addresses from the counter for refreshing the memory array. The second pair of inputs to the multiplexing means comprises memory update addresses for writing new information into the memory. A third pair of inputs to the multiplexing means performs two functions. The first function enables the multiplexing means to output either the update addresses or the refresh addresses depending on the state of such inputs. The second function of the third pair of inputs is to identify the output of said multiplexing means as either a row address or a column address to the associated memory. The apparatus and technique disclosed herein is especially pertinent when a 'nibble mode' dynamic RAM is used as the memory.

Dual purpose screen/memory refresh counter

A full page display device for a text processing system in which a text stream input by way of a keyboard is stored and displayed to the operator on a display device including a cathode ray tube, the electron beam of which is modulated and scanned in a series of horizontal traces to produce an image of the text line on the screen of the display device. The system comprises storage means which includes a plurality (four in a specific embodiment) of separate storage devices. In the specific embodiment, when the storage devices are accessed for display, one character is accessed simultaneously from the same location in each of the storage devices. The data is latched and coupled to a character generator to read out character dot pattern data which is latched and then interleaved with the data from other accessed character data by transferring the data one character at a time in parallel to a serializer. The data out of the serializer forms a serial bit stream which is coupled to the cathode ray tube to modulate the intensity of the beam in synchronism with the sweep to display the selected character data.

Full page display apparatus for text processing system

Growing community of inventors

Georgetown, TX, United States of America

James D Wagoner