Altera Corporation

Sandisk Corporation

Hewlett-packard Company

Altera Corporaton

James D Sansbury

Raminda U Madurawe

John E Turner

Rakesh H Patel

Myron Wai Wong

John C Costello

Peter J Wright

Christopher J Pass

Sau C Wang

Kevin A Norman

Alan Louis Herrmann

Richard G Smolen

Minchang Liang

Matthew C Hendricks

Juliana Manoliu

Behzad Nouban

Laurence G Walker

Bruce F Mielke

Robert D Rung, Jr

Bruce E Mielk

Bruce E Mielke

A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Nonvolatile memory cell with low doping region

Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.

Apparatus and method for margin testing single polysilicon EEPROM cells

A memory cell ( ) used to store data in an integrated circuit. The memory cell ( ) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell ( ) is about VDD and a logic low output is about VSS. The memory cell ( ) of the present invention includes a programmable memory element ( ). In one embodiment, the programmable memory element ( ) is coupled between supply voltage ( ) and an output node ( ). A pull-down device ( ) is coupled between another supply voltage ( ) and the output node ( ). The memory cell ( ) may be used to store the configuration information for a programmable logic device ( ).

Nonvolatile configuration cells and cell arrays

A programmable impedance element ( ) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device ( ), and is nonvolatile.

Programmable impedance device

A nonvolatile memory cell (500) has multiple oxide thicknesses, a tunnel oxide portion (625) and thicker gate oxide portion (630). The memory cell (500) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. Techniques for operating programming, erasing, and characterizing the memory cell with multiple oxide thicknesses are discussed.

Nonvolatile memory cell with multiple gate oxide thicknesses

A programmable impedance element (,) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (,), and is nonvolatile.

A memory cell (,) used to store data in an integrated circuit. The memory cell (,) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (,) is about VDD and a logic low output is about VSS. The memory cell (,) of the present invention includes a programmable memory element (,). In one embodiment, the programmable memory element (,) is coupled between supply voltage (,) and an output node (,). A pull-down device (,) is coupled between another supply voltage (,) and the output node (,). The memory cell (,) may be used to store the configuration information for a programmable logic device (,).

Techniques are used to evaluate margin of programmable memory cells. In particular, techniques are used to measure negative erased threshold voltage levels. Techniques are used to increase the longevity and reliability of memory cells by adjusting a window of memory cell operation

Evaluation of memory cell characteristics

A nonvolatile memory cell (,) has a read device (,), program device (,), and tunnel diode (,). A write control line (WC) is directly coupled to the tunnel diode (,). The memory cell (,) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, half-select voltages are used on the write control (WC) and control gate lines (CG) for unselected memory cells to prevent disturb and minimize oxide stress.

Compact electrically erasable memory cells and arrays

A nonvolatile memory cell (,) has multiple oxide thicknesses, a tunnel oxide portion (,) and thicker gate oxide portion (,). The memory cell (,) may be used to form compact arrays of memory cells to store logical data. During programming of a selected memory cell, unselected memory cells are not disturbed, and oxide stress for the unselected memory cells is minimized. Techniques for operating programming, erasing, and characterizing the memory cell with multiple oxide thicknesses are discussed.

Growing community of inventors

Portola Valley, CA, United States of America

James D Sansbury