International Business Machines Corporation

James D Reid

Chester A Heath

James O Nicholson

Frederick E Strietelmeier

Bradly George Frey

John W Blackledge, Jr

Bechara F Boury

Ronald E Valli

An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Address space architecture for multiple bus computer systems

A computer system having a plurality of devices which transmit and receive information over a channel is presented. The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access. Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit. At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal. All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel. Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique. Thus, each device is dynamically programmable to operate in a linear mode or a fairness mode depending on user and/or application needs. Additionally, each local arbiter includes a circuit which detects whether the device is a burst transfer device or a single transfer device.

Computer system having dynamically programmable linear/fairness priority

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Boynton Beach, FL, United States of America

James D Reid