Georgia Tech Research Corporation

James D Meindl

Muhannad S Bakir

Thomas K Gaylord

Paul Albert Kohl

Kevin P Martin

Elias N Glytsis

Chirag Suryakant Patel

Hollie K Reed

Stephen M Schultz

Tony Mule&prime;

Tony Mule′

Calvin Richard King, Jr

Justin L Stay

Hiren D Thacker

Deepak Chandra Sekar

Agnes M Padovani

Bing Dang

Tony Mule

Sue Ann B Allen

Jesal Zevari

Ricardo Villalaz

Jonathan S Maikisch

Oluwafemi O Ogunsola

An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.

Air-gap C4 fluidic I/O interconnects and methods of fabricating same

High-dielectric-constant (k) materials and electrical devices implementing the high-k materials are provided herein. According to some embodiments, an electrical device includes a substrate and a crystalline-oxide-containing composition. The crystalline-oxide-containing composition can be disposed on a surface of the substrate. Within the crystalline-oxide-containing composition, oxide anions can form at least one of a substantially linear orientation or a substantially planar orientation. A plurality of these substantially linear orientations of oxide anions or substantially planar orientations of oxide anions can be oriented substantially perpendicular or substantially normal to the surface of the substrate such that the oxide-containing composition has a dielectric constant greater than about 3.9 in a direction substantially normal to the surface of the substrate. Other embodiments are also claimed and described.

High dielectric constant insulators and associated fabrication methods

Photo-masks for fabricating surface-relief grating diffractive devices and methods of fabricating surface-relief grating diffractive devices are described. The photo-mask can include refractive elements and/or diffractive elements contained in or on a body element. The photo-mask can be used to simultaneously produce multiple surface-relief grating diffractive devices in a recording material. The photo-mask enables the surface-relief grating diffractive devices to be produced in large quantities while significantly reducing the cost and labor required.

Photo-masks and methods of fabricating surface-relief grating diffractive devices

Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes. Other embodiments are also claimed and described.

3-D ICs with microfluidic interconnects and methods of constructing same

Improved photo-masks for use in fabricating periodic structures are disclosed herein. Methods of making periodic structures, as well as the periodic structures fabricated therefrom, are also disclosed. The photo-mask can include a body element and one or more sets of diffractive elements and/or refractive elements disposed on the body element or within the body element. Each set of diffractive elements and/or refractive elements can be configured to produce four non-coplanar beams of light when a beam of light is passed through it. Each set of four non-coplanar beams of light can be used to interferometrically produce a specific periodic structure at a specific location within a photosensitive recording material.

Photo-masks and methods of fabricating periodic optical structures

Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.

High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof

Probe modules, methods of use of probe modules, and methods of preparing probe modules, are disclosed. A representative embodiment of a probe module, among others, includes a redistribution substrate and a probe substrate interfaced with the redistribution substrate. The probe substrate is operative to test at least one signal of at least one optoelectronic device under test. The probe substrate is operative to interface with electrical and optical components.

Probe module for testing chips with electrical and optical input/output interconnects, methods of use, and methods of fabrication

Input/output (I/O) interconnects, fluidic I/O interconnects, electrical, optical, and fluidic I/O interconnects, devices incorporating the I/O interconnects, systems incorporating the I/O interconnects, and methods of fabricating the I/O interconnects, devices, and systems, are described herein.

Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.

Devices having compliant wafer-level packages with pillars and methods of fabrication

Devices and systems having one or more of the following components: a compliant pillar with a modified tip surface (non-flat tip) and a corresponding compliant socket; an optical/electrical I/O interconnect and a corresponding compliant socket; a lens/waveguide optical pillar, a polymer bridge, and an L-shaped pillar, are described herein. In addition, methods of making these components and methods of using these components are disclosed herein.

Dual-mode/function optical and electrical interconnects, methods of fabrication thereof, and methods of use thereof

Systems and methods for back-of-die, through-wafer guided-wave optical clock distribution systems (networks) are disclosed. A representative back-of-die, through-wafer guided-wave optical clock distribution system includes an integrated circuit device with a first cladding layer disposed on the back-side of the integrated circuit device, and an core layer disposed on the first cladding layer. The core layer, the first cladding layer, or the second cladding layer can include, but is not limited to, vertical-to-horizontal input diffraction gratings, a horizontal-to-horizontal diffraction gratings, and horizontal-to-vertical output diffraction gratings.

Back-side-of-die, through-wafer guided-wave optical clock distribution networks, method of fabrication thereof, and uses thereof

Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package

Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.

Growing community of inventors

Marietta, GA, United States of America

James D Meindl