Apple Inc.

Broadcom Corporation

Nvidia Corporation

Miradia Inc.

Apple Computers Inc.

James D Kelly

William T Krein

Charles M Flaig

William Henry Radke

Ziyad Sami Hakura

Emmett Michael Kilgariff

Dale L Kirkland

Michael C Shebanow

Johnny S Rhoades

Steven J Sfarzo

Michael L Regal

Manu Gulati

Steven E Molnar

Joseph Byron Rowlands

Laurent Rene Moll

John C Difonzo

R Stephen Polzin

Robert L Bailey

Ronald Ray Hochsprung

Koray Oner

Shoucheng Zhang

Chi Xu

Mehrdad Hooshmand

Lesley A Bird

Liangyuan Xiang

Keeley M Maher

This application relates to a portable electronic device. The portable electronic device includes a housing including (i) a lower case, and (ii) an upper case pivotally coupled to the lower case with a hinge assembly. The housing includes a processor capable of providing instructions, an operational component in communication with the processor, where the processor is capable of executing a function, and a magnetic detection system included within the hinge assembly. The magnetic detection system includes a magnetic element capable of generating a magnetic field, and a magnetic sensor capable of determining an angle between the lower case and the upper case based on the magnetic field, where when the processor determines that the angle between the lower case and the upper case satisfies a predetermined threshold angle, the processor provides the instructions to the operational component to execute the function.

Integrated sensor in clutch assembly for determining angle of display

Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.

Dual-sided memory module with channels aligned in opposition

One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Distributing primitives to multiple rasterizers

A mechanism is provided for reorderingReorderingbus transactionsto increaseincreasesbus utilizationin a computer system in whichwherea split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In; inanother embodiment,the system is more loosely coupled withonly mastersbeingareordered. Greater bus utilization is thereby achieved. To avoid deadlock, transactions begun on the split-transaction bus are monitored. When a combination of transactions would,result in deadlockif a predetermined further transaction were to begin,result in deadlock,this condition is detected. In the more tightly coupled system, the predetermined further transaction, if itisrefused ifrequested,is refused, therebyavoiding deadlock. In the more loosely-coupled system, the flexibility afforded by unordered slaves is taken advantage of to, in the typical case,reorder the transactions and avoid deadlock without killing any transaction. Where a data dependency exists that would prevent such reordering, the furthertransactionstransactionis killed as in the more tightly-coupled embodiment. Data dependencies are detected in accordance with address-coincidence signals generated by slave devices on a cache-line basis.In accordance with a further optimization, at least one slave device (e.g., DRAM) generates page-coincidence bits. When two transactions to the slave device are to the same address page, the transactions are reordered if necessary to ensure that they are executed one after another without any intervening transaction. Latency of the slave is thereby reduced.

Bus transaction reordering in a computer system having unordered slaves

A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock domains to control timing of data transfer from one to the other, by selecting a pattern which identifies when data is made transparent for the transfer. The gearbox allows a number of clock ratios to be selected, so that a particular clock ratio between the two domains may be readily selected in the gearbox for the data transfer.

Apparatus and method to interface two different clock domains

A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

Memory controller configurable to allow bandwidth/latency tradeoff

A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Apparatus and method to switch a FIFO between strobe sources

A spatial light modulator for use in projection display applications is provided. The spatial light modulator includes a substrate including a plurality of electrically active circuits and an electrode layer electrically coupled to at least one of the plurality of electrically active circuits. In one embodiment, the electrode layer includes a semi-continuous layer with at least one optical path. The spatial light modulator also includes a shielding layer electrically isolated from the electrode layer and disposed between the substrate and the plurality of electrically active circuits and an electrical connector coupling the shielding layer to a reference potential. In a specific embodiment, the shielding layer of the spatial light modulator converts incident light energy to electrical current and routes the current back to a source. In another specific embodiment, the shielding layer converts electrical field disturbance to electrical current and routes the current back to a source.

Memory cell dual protection

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Addressing scheme supporting variable local addressing and variable global addressing

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Aptos, CA, United States of America

James D Kelly