Intel Corporation

International Business Machines Corporation

James D Allen

Darrell D Boggs

Michael D Upton

David W Burns

David J Sager

Elmoustapha Ould-Ahmed-Vall

Bret L Toll

Jesus Corbal

Jason W Brandt

Edward Thomas Grochowski

Stephen H Gunther

David B Papworth

Robert S Chappell

Thomas R Huff

Buford M Guy

Deepak Limaye

Christopher J Hughes

Lihu Rappoport

Alan Beecher Kyker

Ronak Singhal

James Edward Phillips

Douglas Hanthorn

Seyed Yahya Sotoudeh

Teresa Lynn Davis

Vedvyas Shanbhogue

Daniel Cutter

Venkateswara Rao Madduri

Amit A Merchant

Jonathan D Combs

Jose Niell

Stephen J Robinson

Arvind Raman

Jeffrey G Wiedemeier

Jonathan Jay Tyler

Jeff Huxel

Shadi T Khasawneh

Steven A King

Krishnakumar Ganapathy

Kulin N Kothari

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

Software visible and controllable lock-stepping with configurable logical processor granularities

Zeroing a cache line

In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.

Providing snoop filtering associated with a data buffer

A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Micro-architecture for eliminating MOV operations

Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Dynamic selection of execution stage

In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Method and apparatus for assigning thread priority in a processor or the like

Traffic signal timing may be altered as a function of determining occluded signal viewing. More particularly, processing units may determine that a view of a traffic signal by a person is obstructed by a vehicle located on a first ingress path to a roadway intersection with a second ingress path. The traffic signal controls the right of way of the first ingress path, and the person with the obstructed view is travelling along the first ingress path toward the intersection and is located behind the vehicle relative to a view sightline of the person to the traffic signal. In response to the occluded view determination, a transition of the traffic signal may be delayed from a current visual display of a proceed signal to a subsequent visual display of a stop signal, until an end of a delay period.

Control of traffic signal due to obstructed view

Traffic signal timing may be altered as a function of determining occluded signal viewing. More particularly, processing units may determine that a view of a traffic signal by a person is obstructed by a large vehicle located on a first ingress path to a roadway intersection with a second ingress path. The traffic signal controls the right of way of the first ingress path, and the person with the obstructed view is travelling along the first ingress path toward the intersection and is located behind the large vehicle relative to a view sightline of the person to the traffic signal. In response to the occluded view determination, a transition of the traffic signal may be delayed from a current visual display of a proceed signal to a subsequent visual display of a stop signal, until an end of a delay period.

A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to generate a final linear address and an initial linear address after receiving at least three input source values. An index generation unit coupled to the AGU is to generate a set-index value using the bits of at least the three input source values or the bits of the initial linear address even before the bits of the initial linear address are adjusted for carry. A TLB is to generate a physical address using the final linear address and an entry indexed by the set-index value.

Indexing a translation lookaside buffer (TLB)

Shuffleboard section

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Portland, OR, United States of America

James D Allen