Cypress Semiconductor Corporation

Inmos Limited

Inova Microelectronics Corporation

James D Allan

Jayant Ashokkumar

David W Still

John J Silver

Keith A Ford

Robert W Manning

Iulian Constantin Gradinariu

Stefan-Cristian Rezeanu

Sean B Mulholland

Eric Wolf Gross

Vijay Srinivasaraghavan

John Roger Gill

Emad Hamadeh

The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

Method and apparatus to implement a reset function in a non-volatile static random access memory

A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.

Method and apparatus to program and erase a non-volatile static random access memory from the bit lines

A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.

Method and apparatus to program both sides of a non-volatile static random access memory

A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.

Method and apparatus to create an erase disturb on a non-volatile static random access memory cell

An embodiment of an amplifier circuit including a power supply node and an output node is adapted to provide, during operation, an output node voltage ranging to within 0.2 volts of a power supply voltage used during the operation. An embodiment of the circuit includes a differential first stage coupled to the power supply node and providing a pair of first stage outputs for coupling to a differential second stage. In a method of providing an output voltage near the power supply voltage of an amplifier, a first stage output voltage ranging to within a transistor turn-on voltage of the power supply voltage is produced. The first stage output voltage may further be coupled to a second stage of the amplifier, where the coupling may modulate a current flow through a first pair of cascaded transistors. An output node of the amplifier may be arranged between the pair of transistors and the power supply voltage node.

Operational amplifier with extended output voltage range

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to select (i) a read-back address signal or (ii) a data signal as an output signal in response to one or more first control signals. The second circuit may be configured to generate (i) the read-back address signal and (ii) a cycle identification signal in response to an internal address signal and one or more second control signals. The third circuit may be configured to generate one or more I/O control signals in response to the cycle identification signal, where the one or more I/O control signals may determine the format of the output signal.

Circuit, architecture and method for reading an address counter and/or matching a bus width through one or more synchronous ports

An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry. In a further embodiment, a plurality of cells of an asynchronous memory device may be read in parallel and an output signal indicative of a logical combination of logic states of the plurality of cells and a test signal at the speed of the slowest cell access time produced thereby.

Parallel test for asynchronous memory

A memory device includes a memory array having bit line pair interface connections being made alternatively at each side of the array. Column redundancy bit line pairs may be directed to either side of the array. In addition, bit line loads are placed at both ends of respective bit line pairs to improve speed. Stated differently, the memory device includes a bit line pair accessible from either of two sides of the memory array. The array may be one of a number of blocks within the memory device, while the bit line pair may comprise a redundant column bit line pair. The two sides of the memory array from which the bit line pair is accessible may be opposite sides of the array. In addition, the memory device may also include interdigitated bit line pairs within the memory array. One or more bit line pairs, including the above-mentioned redundant column bit line pair, may have bit line loads (e.g., transistors) at each end.

Semiconductor memory with interdigitated array having bit line pairs

An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the fist output signals and to produce second output signals indicative of logic states of the first output signals therefor The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry. In a further embodiment, a plurality of cells of an asynchronous memory device may be read in parallel and an output signal indicative of a logical combination of logic states of the plurality of cells and a test signal at the speed of the slowest cell access time produced thereby.

A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise 'illegal' operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.

Test mode entrance through clocked addresses

A block selecting scheme for a memory device. The block selecting scheme includes a sub word line driver circuit having multiple sub word line drivers and an inverter circuit. For one embodiment, the sub word line driver circuit includes four sub word line drivers. Each sub word line driver is used to select the sub word line for a corresponding memory block. Each of the sub word line drivers is coupled to a global word line via the inverter circuit. Furthermore, each of the sub word line drivers operates as an inverter. By coupling the global word line and each of the sub word lines via two inversion circuits, the global word line and the sub word lines are typically at the same voltage level. Thus, the deleterious effect of shorting between adjacent global word lines and sub word lines is substantially reduced. Furthermore, by grouping more than two sub word line drivers together, the overall die size of the memory device may be reduced.

Sub-word line driver circuit for memory blocks of a semiconductor memory

The invention provides an apparatus and method for reducing the access time of a memory cell after a write operation. A one-shot generation circuit generates a one-shot pulse in response to a falling edge on an external write line or a change in the state of the data signal during an inactive state of the write signal. This one-shot pulse then controls writing data into a static memory cell. Since it is not necessary to wait for the write external line to go high before triggering the end of the internal write pulse, the access time of the static memory device is reduced.

Apparatus and method for reducing the access time after a write

An input buffer has input and output inverters. An n-channel transistor is coupled as a source follower between the inverters. The buffer receives a TTL input and provides a CMOS output. The source follower transistor has a large channel width and provides substantial pullup. The output inverter stage can be made larger. A p-channel transistor in parallel with the n-channel source follower transistor permits the internal node to reach a full Vcc level. Another n-channel transistor driven by the input signal permits the node to reach ground.

Source follower CMOS input buffer

In a DRAM, current surges during sense and restore operations are compensated. Peak current through sense amplifiers is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function. The second sensing signal timing is not determined by the first sensing signal.

Dram current control technique

A CMOS substrate bias generator including a PMOS charge pump and a regulator for controlling the operation of the substrate bias generator. The substrate bias generator further includes an input circuit, a reference circuit to provide a reference voltage, a comparison circuit to compare voltage levels between the input and the reference circuit, and output circuitry to provide a signal from the comparison circuitry to the substrate bias generator. The comparison circuitry further includes hysteresis circuitry tending to preserve voltage at a node in the comparison circuit despite an imbalance between the input circuit and the reference circuit.

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Colorado Springs, CO, United States of America

James D Allan