Hewlett-packard Development Company, L.p.

Hewlett-packard Company

James Curtis Farmer

Kent Andrew Dickey

A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.

Circuit for allowing data return in dual-data formats

A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor of thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock may be run throughout the system to integrated circuits. The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock. This ensures that the event will also be seen on a rising edge of every other system clock, which makes the event appear at the same time throughout the system. By ensuring that an asynchronous function, such as a reset function, appears at the same time throughout the system, the system becomes repeatable. That is, the clock states will be the same every time an asynchronous event is released to the system.

Method for triggering an asynchronous event by creating a lowest common denominator clock

A method and apparatus for detecting, enabling and disabling deadlock errors, and recording deadlock information in the error logs of a data processing system even after a power-on reset. One embodiment of the invention involves a method for indicating a deadlock error in a data processing system capable of having a deadlock error. The method includes indicating that an error is a deadlock error, providing an input signal to set a deadlock error enable circuit having an output signal indicating that the deadlock error will cause a deadlock reset signal to be asserted, logically ORing deadlock error signals to produce a deadlock output; and logically ANDing the deadlock output and the output signal of the deadlock error enable circuit to produce the deadlock reset signal. A second embodiment of the invention involves a data processing system or an error log system, capable of having a deadlock error selected from several deadlock errors. The data processing system or error log system includes a deadlock error enable circuit having an output signal indicating that the deadlock error will cause a deadlock reset signal to be asserted, a first combinational logic circuit to logically OR the deadlock signals, having a deadlock output, and a second combinational logic circuit to logically AND the deadlock output of the first combinational logic circuit and the output signal of the deadlock error enable circuit, to produce the deadlock reset signal.

Apparatus and method for detecting, diagnosing, and handling deadlock errors

A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

System and method to protect vital memory space from non-malicious writes in a multi domain system

An apparatus and method using a set of registers for indicating multiple error levels in a data processing system, recording information for each error level, and providing an order register to allow software or a user to determine the sequence order in which errors occurred. One embodiment of the invention involves a method for indicating errors in a data processing system with multiple error levels, indicating that an error corresponds to an error level, representing the error with a set of memory cells, and recording the order in which the error has occurred. A second embodiment of the invention involves a data processing system, including a primary error log to record an error, and at least one error logging register that can record information about the error. A third embodiment of the invention involves an error log system, including a primary error log to record an error having a corresponding error level, an error logging register corresponding to one of a plurality of error levels to record information about the error, and an error order register to record information about the order of occurrence of the error.

Apparatus and method for providing error ordering information and error logging information

A system and method is described in which protected memory writes are achieved in single transaction without leaving open a window in time for erroneous data to corrupt space in a target register. A single data packet preferably includes both user data to be written to a target storage device or location as well as the key data for authorizing the writing of such user data. Key data is preferably calculated by manipulating user data contained in the same packet or transmission thereby simplifying a verification process conducted the controller associated with target storage location.

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Sunnyvale, CA, United States of America

James Curtis Farmer