Dell Products Inc.

Emc Corporation

Emc IP Holding Company LLC

James Creighton Tryhubczak

Stephen Edward Strickland

Steven D Sardella

John Victor Burroughs

Brian K Campbell

Ryan Cartland McDaniel

Ofer Porat

Clayton Alan Curry

John Phinney

Wuck Foo Wong

Michael Alexander Raineri

Jim H Street

A system for controlling data communications, comprising an enclosure management processor configured to generate a peripheral component interconnect express reset command and a chip reset command. A re-timer configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command. The communications port configured to reset in response to a control signal from the re-timer.

PCIe link management without sideband signals

Identifying a first controller and a second controller each connected to a computing device over a first serial bus for monitoring of the computing device; allocating, at the first controller, i) a first internal register bit of a first register indicating an arbitration status of the first controller with respect to the computing device and ii) a second internal register bit of the first register indicating an arbitration status of the second controller with respect to the computing device; allocating, at the second controller, i) a third internal register bit of a second register indicating the arbitration status of the first controller with respect to the computing device and ii) a fourth internal register bit of the second register indicating the arbitration status of the second controller with respect to the computing device.

Arbitrating serial bus access

Data storage system power shedding for vaulting and/or backup is provided herein. A data storage system can include a processor that executes computer-executable components, at least one memory, and a basic input/output system device that stores respective ones of the computer-executable components executed by the processor. The computer-executable components comprise a power monitor component that monitors an input alternating current power level of the data storage system, a processor management component that causes the processor to transition from a multiple-core operating mode to a single-core operating mode in response to an indication from the power monitor component that the input AC power level has decreased below a threshold, and a backup component that initiates a transfer of data stored by the at least one memory to at least one backup storage device in response to the processor being configured to operate in the single-core operating mode.

Data storage system power shedding for vault

Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Interface for establishing operability between a processor module and input/output (I/O) modules

A system having memory modules for storing nibbles of a word. The nibbles include an error correction/detection code. A memory controller is response to clock pulses to produce a read command. A synchronizer is responsive to the read nibbles and an associated read strobe signal for synchronizing the read nibbles and the read strobes to the clock pulses. A detection section is responsive to the clock pulses and the read command for producing a time window representative of a time duration during which each of the read strobes is expected. The detection system is responsive to each one of the read strobes and the produced time window for producing, for each one of the read strobes, a corresponding one of a plurality of NIBBLE ERROR signals. Each one of the NIBBLE ERROR signals indicates whether the corresponding one of the read strobes is within the produced window or is absent from such window.

Memory system

Growing community of inventors

Cumberland, RI, United States of America

James Creighton Tryhubczak