Northern Lights Semiconductor Corp.

James Chyi Lai

Tom Allen Agan

Vicki Wilson

Guoqing Zhan

Ray Buske

Kai Chun Fong

Kuang-Lun Chen

Chien-Chiang Chan

Chien-Teh Kuo

This invention discloses a load system for loading an Mcap energy storage module to an apparatus, comprising: a storage unit and a load unit. The storage unit further comprises: a first housing part and a seal for sealing the first housing part. The first housing part includes four side walls, a bottom wall and a first opening. A plurality of Mcap cell are disposed in the first housing part through the first opening. A first electrode formed in a side wall. A second electrode formed in another side wall facing the first side wall. The load unit comprises a second housing part and a seal for sealing the second housing part. The storage unit is loaded into the second housing part through the second opening.

Load system for an Mcap energy storage module

An energy storage system includes a battery charger and energy storage devices. The battery charger is connected to a DC/AC current source. The energy storage devices are coupled between the battery charger and subsystems respectively. Each of the energy storage devices includes a magnetic capacitor (MCAP) and an over current protection device (OCPD). MCAPs are charged by the battery charger and supply the electric power to subsystems connected the energy storage devices. OCPDs detect current from MCAPs to subsystems and protect subsystems from excessive currents of voltages.

Energy storage system

A MRAM memory and process thereof is described. A GMR magnetic layer is patterned to form a memory bit layer and an intermediate conductive layer. The intermediate conductive layer is disposed between two conductive layers such that shallow metal plugs can be utilized to interconnect the intermediate conductive layer and the conductive layers. Thus, a conventional deep tungsten plug process, interconnecting two conductive layers, is eliminated.

Magnetoresistive random access memory with improved layout design and process thereof

A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for routing magnetic gates in the first and second logic gate layers, wherein the first logic gate layer, the second logic gate layer, and the routing layer are electrically connected by vias.

Integrate circuit chip with magnetic devices

An apparatus for storing electrical energy is provided. The apparatus includes a first magnetic layer, a second magnetic layer, and a dielectric layer. The first magnetic layer has a first surface with saw tooth roughness; the second magnetic layer has a second surface with saw tooth roughness; and the dielectric layer is configured between the first magnetic layer and the second magnetic layer. The dielectric layer is arranged to store electrical energy; the first magnetic layer and the second magnetic layer are arranged to prevent electrical energy leakage; and the saw tooth roughness on the first surface and the second surface is designed to increase the capacitance of the apparatus.

Apparatus for storing electrical energy

A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer.

Interconnect for a GMR memory cells and an underlying conductive layer

A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Magnetic transistor structure

A variable timing system for a magnetoresistive random access memory circuit (MRAM IC) is embedded in an MRAM IC and includes a number of timing control circuits, where each timing control circuit generates a timing control signal. A number of variable timing circuits are each coupled to receive at least two of the timing control signals, and each of the number of timing circuits outputs a variable timing in response to the timing control signals. At least one MRAM timing driver is connected to receive the variable timing.

Method for generating adjustable MRAM timing signals

A giant magnetoresistance (GMR) pad on the same level of GMR memory bit layer is used as an intermediate connection for plugs between the GMR pad and an underlying diffusion metal layer. A single large power metal plug is used to connect the GMR pad and the overlying power plane metal.

Interconnect connecting a diffusion metal layer and a power plane metal and fabricating method thereof

An integrated circuit with magnetic memory has a silicon transistor layer, at least one magnetic memory layer, and a metal routing layer. The silicon transistor layer is arranged to generate several logic operation functions. The magnetic memory layer is arranged to store the data required by the logic operation functions. The metal routing layer has several conducting lines to transmit the data between the silicon transistor layer and the magnetic memory layer.

Integrated circuit with magnetic memory

A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.

Magnetic transistor

A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended transition detection signal output. The magnetic random access memory has a timing controller with a timing control input connected to the address transition detection signal output. The chip enable input, the chip write enable input, the data bus connection, and the address bus connection are buffered and driven off chip.

MRAM internal clock pulse generation with an ATD circuit and the method thereof

A word line driver and decoder for use in a magnetic memory includes a main word line driver and a sub word line driver that cooperate to drive current on a selected one from a number of the magnetic memory's word lines. The main word line driver and sub word line driver employ pull up and pull down transistors that configured to drive current on the selected word line in either a read or write '0' direction or a read or write '1' direction in response to control signals that allow reliable magnetic memory operation. An address decoder selects and activates a multiplexer in the sub word line driver to coordinate the current drive. The main word line driver employs current mirrors, transistor switches, and logic control to prevent direct Vdd to Vss shorting in transitioning from &#x2018;0&#x2019; and &#x2018;1&#x2019;, and read and write data storage operations.

Word driver and decode design methodology in MRAM circuit

A magnetic AND/NOR circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The 'AND' and 'NOR' logic functions of the binary system can be implemented by the control of these metal devices.

Growing community of inventors

Saint Paul, MN, United States of America

James Chyi Lai