International Business Machines Corporation

James Charles Gregerson

Eric A Foreman

Chandramouli Visweswariah

Peter Anton Habitz

Jeffrey G Hemmett

Nathan C Buck

John Steven Dodson

Patrick James Meaney

Kerim Kalafala

Gary A Van Huben

Eric Eugene Retter

Natesan Venkateswaran

Michael H Wood

Vesselina K Papazova

Glenn David Gilda

Debjit Sinha

Scot H Rider

Lawrence D Curley

Irving G Baysah

Michael Steven Siegel

David James Hathaway

Vladimir P Zolotov

Albert James Van Norstrand, Jr

Howard Hao Chen

Alexander Joel Suess

Tad Jeffrey Wilder

Susan K Lichtensteiger

John P Dubuque

Gregory M Schaeffer

Brian M Dreibelbis

Xiaoyue X Wang

James Patrick Eckhardt

James R Robinson

Tsz-mei Ko

Edward J D'Avignon

Alex Rubin

Norman C Chou

Vladimer Zolotov

Michael A Smoolca

A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Superposition of canonical timing value representations in statistical static timing analysis

Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

Dual asynchronous and synchronous memory system

Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.

Statistical clock cycle computation

Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.

Efficient slack projection for truncated distributions

Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

Chip design and fabrication method optimized for profit

Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.

Methods for practical worst test definition and debug during block based statistical static timing analysis

Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

Method, computer program product, and apparatus for static timing with run-time reduction

A distributed file system for a multi-processor system having multiple nodes, each node having a client processor and a client disk. The nodes are connected to a communications fabric for passing files between the nodes. One of the nodes acts as a server for passing files from the server to any of the other nodes. When a client processor reads a file on its client disk, the client processor obtains the server copy of the file and installs it on the client disk if the server copy of the file is more current, before the read operation. Provision is also made for atomically providing upgrades of application files to the client disks. When the client processor writes to a file, it sets a write flag in the file so that the file thus written to by the client processor is invisible to file operations from the server and the other nodes. The disclosed file system is particularly useful for systems administration of a multi-processor system having a single point of systems software install.

Client server based multi-processor file system wherein client files

A method and system for enhancing processing efficiency in a data processing system which includes multiple scalar instruction processors and a vector instruction processor. An ordered sequence of intermixed scalar and vector instructions is processed in a nonsequential order by coupling those instructions to selected processors. As each instruction is finished an indication of that state is stored within a finish instruction array. The first vector instruction within the ordered sequence is initiated within the vector instruction processor only after an indication that each scalar instruction preceding the first vector instruction is finished. A vector advance signal is generated by the vector instruction processor each time processing of a vector instruction is initiated. A subsequent vector instruction is then initiated when the vector processor assets are available only in response to the presence of the vector advance signal and an indication that all scalar instructions which proceed the subsequent vector instruction within the ordered sequence have finished, without encountering an exception. In this manner, chained processing of vector instructions may be accomplished by initiating processing of a subsequent vector instruction only after possible interruption by a scalar instruction exception is no longer possible.

Method and system for nonsequential execution of intermixed scalar and

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James Charles Gregerson