Intel Corporation

James Charles Abel

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Bret L Toll

Edward Thomas Grochowski

Milind Baburao Girkar

Robert Dale Cavin

Andrew Thomas Forsyth

Dennis Ryan Bradford

Jonathan Cannon Hall

Suleyman Sair

Seth Abraham

Charles R Yount

Jesus Corbal San Adrian

Sridhar Samudrala

Jeffrey G Wiedemeier

Lisa K Wu

Santiago Galan Duran

Roger Espasa Sans

Mark Jay Charney

Brad D Hinkle

Jason W Brandt

Hong Wang

Baiju V Patel

Per H Hammarlund

Scott Dion Rodgers

Prashant Sethi

Gautham N Chinya

John Thomas Shen

Shivnandan D Kaushik

Bryant E Bigbee

Xiang Chris Zou

Richard A Hankins

James Paul Held

Douglas M Carmean

Michael A Julier

Sanjiv M Shah

John L Reid

Ryan N Rakvic

Jonathan Jay Tyler

David K Poulsen

Derin C Walters

Mark Charney

Graham S Tubbs

Jacob K Gotwals

Nathanael K Brown

Nikolay Degtyarenko

Robert C Valentine

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

Vector friendly instruction format and execution thereof

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Sequencer address management

Method, apparatus, and program means for performing a packed multiply high with round and shift operation. The method of one embodiment comprises receiving a first operand having a first set of L data elements. A second operand having a second set of L data elements is received. L pairs of data elements are multiplied together to generate a set of L products. Each of the L pairs includes a first data element from the first set of L data element and a second data element from a corresponding data element position of the second set of L data elements. Each of the L products are rounded to generate L rounded values. Each of said L rounded values are scaled to generate L scaled values. Each of the L scaled values are truncated for storage at a destination. Each truncated value is to be stored at a data element position corresponding to its pair of data elements.

SIMD integer multiply high with round and shift

Pixel values of an image are loaded into main memory and cache of a computer system. Two different instructions are used to load pixel values of the image from the cache to a set of registers in a processor of the system. A first one is used when loading an operand (containing pixel values) that is aligned with a cache line boundary of the cache. A second instruction is to be used when loading an operand (containing pixel values) that is not aligned with the cache line boundary. The second instruction can execute a cache line split without a significant performance penalty relative to execution of the first instruction. Other embodiments are also described and claimed.

Image processing using unaligned memory load instructions

A system and a method of automatically prioritizing and analyzing performance data for one or more system configurations are provided. Performance data is obtained about a system using a first tool. The performance data is sorted by a number of contexts, each context divided into a number of sub-contexts. The performance data for at least one sub-context is automatically prioritized using a pre-determined criteria. An insight is obtained using a second tool for at least one sub-context based on the prioritized performance data. An advice associated with that insight is obtained using the second tool.

Method and system for automatically prioritizing and analyzing performance data for one or more, system configurations

A method for computing a decimation-in-time Fast Fourier Transform of a sample is provided, the method including inputting first 2B-bit values representing the sample into a radix-4 first section of the decimation-in-time Fast Fourier Transform and performing first complex 2B-bit integer additions and subtractions on the first 2B-bit values to form second 2B-bit values, without performing a multiplication. The method also includes rounding the second 2B-bit values to form B-bit values output from the radix-4 first section of the decimation-in-time Fast Fourier Transform.

Reducing peak spectral error in inverse Fast Fourier Transform using

A function coprocessor for a processor having a first type of coprocessor interface is described. The function coprocessor includes a subprocessor and program memory coupled to the subprocessor. A data memory stores data from the processor in response to a first control signal. The data memory has m ports coupled to the subprocessor for providing up to m operands to the subprocessor per clock cycle. The function coprocessor also includes a function coprocessor interface compatible with the first type of coprocessor interface for coupling to the processor. The function coprocessor interface generates the first control signal in response to interface signals received from the coprocessor interface of the processor. The function coprocessor interface provides handshake signals to the coprocessor interface of the processor including a busy signal, an error signal, and a processor extension request signal.

Function coprocessor

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Phoenix, AZ, United States of America

James Charles Abel