Ansaldo Sts Usa, Inc.

James C Werner

William A Sharp

John E Lemonovich

Lawrence A Weber

Zhu Ding

William J Moltz

James Brown

Sean P Berecek

A system for serially transmitting vital data includes first and second processors to determine first and second data, a serial communication apparatus to input third data and output serial data based upon the third data, and a memory having first and second ports accessible by the first and second processors, a first memory writable by the first processor and readable by the second processor, and a second memory writable by the second processor and readable by the first processor. The first and second processors store the first and second data in the first and second memories, cooperatively agree that the first data corresponds to the second data, and responsively cause the apparatus to employ: one of the first and second data as the third data, or parts of the first and second data as the third data, and output the serial data based upon the third data.

System and method to serially transmit vital data from two processors

An output apparatus includes a first source of a first signal having a first state or a different second state; a second source of a second signal having a first state or a different second state; and a circuit structured to output a vital output including a first state when the first state of the first signal corresponds to the first state of the second signal and, otherwise, including a different second state. At least one of the first signal and the second signal is a static signal. The other one of the first signal having the first state and the second signal having the first state is a dynamic signal. When at least one of the first signal has the different second state of the first signal and the second signal has the different second state of the second signal, the vital output includes the different second state.

Output apparatus to output a vital output from two sources

A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.

Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays

A light emitting diode (LED) circuit includes first and second terminals, a forward circuit including a number of LEDs electrically connected in series, and a forward steering diode electrically connected in series with the LEDs. The series combination of the forward steering diode and the LEDs is electrically connected between the first and second terminals, and is structured to conduct current in a first direction with respect to the first and second terminals in order to illuminate the LEDs. A reverse circuit includes a resistor, and a reverse steering diode electrically connected in series with the resistor. The series combination of the reverse steering diode and the resistor is electrically connected between the first and second terminals, and is structured to conduct current in an opposite second direction with respect to the first and second terminals such that the LEDs are not illuminated. An LED drive circuit is also disclosed.

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Oakmont, PA, United States of America

James C Werner