Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Dialog Semiconductor (uk) Limited

Philips Semiconductor, Inc.

James C Steele

David K Cassetti

Swaroop Adusumilli

Rodney J Pesavento

Philip Wszolek

Brian N Fall

Gary A Walker

Mark Mercer

Barry M Davis

Aravind Mangudi

Nick Richardson

David R Evoy

John William Kesterson

Gary D Hicok

Lonnie Calvin Goff

Joseph Alan Thomsen

Desi Rhoden

Taek Chang

Bill McKillop

Mike Crews

George Crouse

A multi-level power converter and a method using first, second, third and fourth switching elements, an inductor, and a flying capacitor are presented. A first terminal of the inductor may be connected to a switching terminal connecting the second and third switching elements. A first terminal of the flying capacitor may be connected to a terminal connecting the first and second elements. A second terminal of the flying capacitor may be connected to a terminal connecting the third and fourth switching elements. The multi-level power converter may have a first feedback circuit to generate control signals for setting the switching elements in a plurality of switching states for regulating an output voltage or an output current. The converter may have a second feedback circuit to generate control signals to allow the flying capacitor to be charged or discharged using an inductor current flowing through the inductor.

Multi-level power converter with light load flying capacitor voltage regulation

A multi-level buck converter is provided with seamless transitions back and forth from synchronous to asynchronous low dropout modes of operation.

Asynchronous dropout transition for multi-level and single-level buck converters

A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.

Arrangement and method for accessing data in a virtual memory arrangement

An arrangement controls an IC designed with multiple &ldquo;core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

Method and arrangement for controlling multiple test access port control modules

An arrangement controls an IC designed with multiple &ldquo;core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.

Method and arrangement for controlling multiply-activated test access port control modules

An arrangement controls an IC designed with multiple &ldquo;TLM'ed core&rdquo; circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple &ldquo;TLM'ed core&rdquo; circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

Method and arrangement for hierarchical control of multiple test access port control modules

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Method and apparatus for direct access to main memory by an I/O bus

The present invention relates to a system and method for starting and maintaining a Central Processing Unit (CPU) clock even though the CPU clock is operating under a Clock Division Emulation (CDE) scheme. Break Events are broken into different groups with each group of Break Events being mapped to a particular programmable event timer. Each of the programmable event timers have an associated time limit which will keep the CPU clock running for a time commensurate with that group of Break Events. When a Break Event occurs, the programmable event timer associated with that particular Break Event will load the corresponding time limit into the programmable event timer. Once loaded, the programmable event timer will keep the CPU clock running during the entire time limit. Only after all of the programmable event timers have counted down will the CPU clock be allowed to stop.

System and method for starting and maintaining a central processing unit

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Method and apparatus for arbitrating access to main memory of a computer

A link system controller is interposed between a PCI bus and the data bus and memory data bus of a personal computer system to normally allow transfer of write information from the PCI bus to DRAM memories on the memory data bus. Whenever a request is made for the transfer of data to the CPU data bus, a CPU bus interface controller requests release of the system from the DRAM controller. The DRAM controller then grants permission or releases control to the CPU bus interface whenever the DRAM controller is not writing data out to the DRAM data bus. When this release is effected, the transfer of write data to the memory data bus is prevented and transfer of data to the CPU data bus is enabled. This prevents simultaneous switching of the devices on both the CPU data bus and the memory data bus, to reduce the generation of noise; so that the operation of the IC system device is not impaired.

Apparatus for granting either a CPU data bus or a memory data bus or a

An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer is not busy. When the deserializer is busy, the bus controller responds to the request from the host system for the current value on the first request pin of the I/O device by waiting for the deserializer to become idle. Upon the deserializer becoming idle, the bus controller forwards to the host system the current value for the voltage on the indicated request pin.

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Chandler, AZ, United States of America

James C Steele