Supercomputer Systems Limited Partnership

Silicon Graphics, Incorporated

James C Rasbold

Don A Van Dyke

Jon A Masamitsu

Robert E Strout, Ii

David M Cox

David A Seberger

Kelly T O'Hair

Timothy J Cramer

Linda J O'Gara

Ashok Chandramouli

Richard E Hessel

George A Spix

Steve S Chen

Gregory G Gaertner

Diane M Wengelski

Keith J Thompson

Jeremiah D Burke

Mark D Johnson

Giacomo G Brussino

Stuart W Hawkinson

Steven G Oslon

David M Barkai

An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes

A method is provided for inserting a path instruction during compilation of computer programs for a processor having multiple functional resources. A path instruction is inserted in the order of object code instruction during the reordering of the instructions in response to a simulation of the run-time environment of the target machine to direct that the path of execution for a subsequent object code instruction be in accordance with an optimum path of execution for the object code instruction as determined by the simulation is different than a preselected default path of execution for an object code instruction for a similar type of object code operation.

Method for inserting a path instruction during compliation of computer

A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is accomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-time environment of the target machine is performed at compile time after the machine instructions have been generated by a compiler, or after instruction generation by an assembler. The present invention rearranges the machine instructions for a basic block of instructions into an order that will result in the fastest execution based upon the results of the simulation of the interaction of the multiple functional resources in the target machine.

Method for optimizing instruction scheduling for a processor having

System and method for controlling a highly parallel multiprocessor using

A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.

Computer with integrated hierarchical representation (IHR) of program

Growing community of inventors

Livermore, CA, United States of America

James C Rasbold