Advanced Micro Devices Corporation

James C Pattison

Richard Thomas Schultz

Jerry D Moench

Edward E Ehrichs

Scott Goad

Vladimir V Shtraikh

James M Hiatt

A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite.

Computer-implemented methods and systems for automatic generation of layout versus schematic (LVS) rule files and regression test data suites

A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns.

Method of creating photolithographic masks for semiconductor device features with reduced design rule violations

In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plurality of semiconductor devices to have a substantially uniform spacing between each gate structure. The method also includes forming a decoupling capacitor region adjacent to the ACLV controlled region. The decoupling capacitor region may include a plurality of capacitor structures each having a conductive structure, such as a polysilicon electrode, for example.

Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit

Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.

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Round Rock, TX, United States of America

James C Pattison