Lsi Corporation

Agere Systems Inc.

James C Parker

Vishwas M Rao

Joseph J Jamann

Clayton E Schneider, Jr

Gregory W Sheets

Benjamin Mbouombouo

Prasad Subbarao

Bruce E Zahn

Martin J Gasper

Stephen A Masnica

Lalita M Satapathy

Todd M Tope

Robert C Sibert

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage.

Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby

A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.

System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same

A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.

Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design tools

A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Hierarchical design flow generator

A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow

Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.

Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method

One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics

A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.

Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.

Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby

Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.

Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.

Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods

Methods for establishing benchmarks and for analyzing benefits associated with voltage scaling are provided. In one embodiment, the method for establishing benchmarks includes: (1) synthesizing a netlist from a RTL of a functional IC design; (2) implementing a layout of an IC from the netlist, wherein the synthesizing and the implementing are performed at designated voltages and frequencies over a voltage and a frequency range, the voltage range including a voltage scaling range and a voltage associated with a designated implementation of the IC; (3) obtaining measurements of at least one voltage scaling metric associated with the IC at each of the designated voltages and frequencies; and (4) normalizing measurements associated with the voltage scaling range to measurements associated with the designated implementation employing a processor to obtain normalized benchmarks for analyzing optimization of the IC associated with voltage scaling. EDA tools may be used for synthesizing, implementing and obtaining.

Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor

One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.

A first integrated circuit design with a first maximum operating frequency is modified to achieve a second integrated circuit design with a second maximum operating frequency. The integrated circuit design comprises an arrangement of cells. Each of these cells drives a signal that propagates through a net of other circuit elements to one or more nodes that are limited by respective signal timing constraints. An analytical cost function is assigned to each of the cells. Each analytical cost function comprises a value for its respective cell that is based on one or more speed-related factors indicative of the impact of the respective cell on the first maximum operating frequency of the first integrated circuit design. One or more of the cells are replaced with different cells based on the determined analytical cost functions.

Growing community of inventors

Zionsville, PA, United States of America

James C Parker