Motorola Corporation

James C Nash

Robert J Skruhak

James B Eifert

John P Dunn

Joseph M Harris, Ii

William C Moyer

Michael D Fitzsimmons

Kuppuswamy Raghunathan

Kirk Samuel Livingston

Michael I Catherwood

Tony Tong-Khay Cheng

Theo C Freund

A data processing system ( ) is configured when coming out of reset using memories of various bit widths ( ). The bytes that make up the reset vector ( ) are fetched individually through separate memory operations from the memory that stores the reset vector. These bytes are stored in a pre-determined manner within each of the potential memory structures ( ) such that predetermined addresses will retrieve the different bytes on the same portion of the data bus. A configuration value ( ) portion of the reset vector ( ) retrieved may be used to configure various parameters ( ) within the data processing system ( ) such that parameters related to the memory or other functional characteristics of the system are initialized. The configuration value ( ) may include data and control sections such that the control section determines how the data section of the configuration value ( ) is applied to various parameters within the data processing system ( ).

Apparatus and method for configuring a data processing system by retrieving a configuration value from storage device using reset vector and configuring parameters after reset

An integrated circuit (10) contains a central processing unit (CPU) (12) and a plurality of memory blocks (26-34) configured into one or more banks of memory. A plurality of power control switches (38-42) are used to dynamically select which of a plurality of external voltage supply signals are provided to power each of the memory blocks (26-34). The power control switches (38-42) may be configured from software via writing the data to a register (24) or can be enabled by test control circuitry (22) or can be automatically enabled in response to VDD power voltage failure. In addition, an intelligent controller can dynamically control the switches in response to execution flow of data accesses and instruction fetches from the memory banks so that only currently accessed memory banks or recently accessed memory banks are activated at a high power level while all other memory banks are in a low power stand-by mode.

Integrated circuit having standby control for memory and method thereof

A method and apparatus for allowing the soft defect detection testing (SDDT) of an memory array (106) of a data processor (100) begins by providing a control value to a memory controller (111). The control value determines whether a switching circuit (104) will apply a VDD power supply voltage from a VDD terminal (132) or a Vstby power supply voltage from a Vstby terminal (130) to a selected portion of the memory array (106). When in an SDDT test mode, the selected portion of the memory array (106) is supplied by the Vstby terminal (130). While being supplied by the Vstby terminal (130), the selected portion of the memory array (106) is SDDT tested by coupling a current detection device to the pin (130) and measuring a current I drawn by the selected portion of the memory array (106).

Method and apparatus for testing on-chip memory on a microcontroller

A data processor has a microcode memory which is reduced in size by sharing word locations having the same contents. When one of the shared word locations is addressed, a control signal is generated and coupled to a select circuit. The select circuit outputs a predetermined operand in place of the contents of the addressed shared word location which can contain a 'do not care' operand value. Selective sharing or combining of the word locations is utilized when structuring the memory to optimize savings in circuit area.

Data processor with microcode memory compression

A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.

Data processor having a multi-stage instruction pipe and selection logic

A memory expansion scheme is provided which permits a program to automatically cross memory bank boundaries, without user intervention. A memory bank address register stores a value corresponding to a selected memory bank (i.e. Bank 0), in a 4-bit subfield (K-Field). In the preferred embodiment, the K-Field is implemented using six (6) bank number registers, each of which is coupled to the corresponding address register, to form a 20-bit (extended) logical address. During an effective address calculation, in the index addressing mode, a 16-bit logical offset address, stored in an offset register, is added to the 20-bit (extended) logical address, by an adder in the ALU. The adder transfers a 20-bit physical address onto an address bus, via an address buffer. When the calculated address crosses a memory bank boundary, the upper four (4) address bits (A.sub.16 -A.sub.19) are automatically updated, thereby enabling the program to cross a memory bank boundary without user intervention. Furthermore, in selected cases, the contents of the bank number register (address bits A.sub.16 -A.sub.19) are automatically updated. Thus, the memory bank expansion scheme provides the capability to automatically cross memory bank boundaries, while automatically updating the information stored in the bank number register.

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Austin, TX, United States of America

James C Nash