Sun Microsystems, Inc.

Oracle America, Inc.

James C Hunt

Thomas Alan Ziaja

Paul J Dickinson

Richard F Avra

Hong Hao

Karl P Dahlgren

Steven C Krow-Lucal

Kanti Bhabuthmal

Murali Gala

Poh-Joo Tan

David L Curwen

Oliver Caty

An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

At-speed scan testing of memory arrays

A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149.1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache. The process of loading the pins with data via boundary scan, and then shifting the data into appropriate caches is repeated for each memory content of the compiled program until all instructions in the program have been loaded into the appropriate caches. Thereafter, the microprocessor is forced into normal execution mode by resetting the microprocessor to reenable its internal clock. Finally, the test program is executed in a manner that allows a user to interact with the microprocessor during execution.

Full-speed microprocessor testing employing boundary scan

Growing community of inventors

Redwood City, CA, United States of America

James C Hunt