Atmel Corporation

James C Hu

Steven J Schumann

Tsung-Ching Wu

Geeng-Chuan Chern

John Y Huang

An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All but opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.

Fabricating a narrow width EEPROM with single diffusion electrode

An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All abut opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.

Narrow width EEPROM with single diffusion electrode formation

A memory cell in an EPROM device which is totally sealed from ultraviolet light by a conductive cover without openings therein for leads to the cell's drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N+ implants, buried N+ layers or N-wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N+ implant or N-well serves as the control gate and is capacitvely coupled to the floating gate via a thin oxide layer in a coupling area.

Sealed charge storage structure

A process of fabricating high performance EPROMs in which memory cell devices and high voltage circuit devices are formed in p-type tub regions of high threshold voltage. The tub regions are formed by implanting boron ions in photolithographically defined memory cell and high voltage device areas of a p-type wafer substrate, then subjecting the substrate to a high temperature drive-in. The N-channel isolation field is formed separately and has a lower threshold voltage than the tub regions. The isolation field is formed by implanting boron ions around all device areas, including low voltage device areas, using a nitride mask and a low implantation energy. The wafer is then subjected to an anneal step followed by a field oxidation step. The memory cell and other MOS devices are finally formed in the appropriate defined regions. Since the isolation field's threshold voltage can be adjusted separately from the tub regions, the threshold voltage of the field can be reduced making it possible to reduce the isolation spacing of low voltage devices, reduce parasitic capacitance and increase device speed.

Growing community of inventors

Saratoga, CA, United States of America

James C Hu