Freescale Semiconductor,inc.

Nxp Usa, Inc.

James C Holt

William C Moyer

Brian Christopher Kahne

Hassan Al Sukhni

Michael D Snyder

David B Kramer

John H Arends

Richard G Collins

Joseph Gergen

Puneet Sharma

Brian C Grayson

Matt B Smittle

Kamal S Khouri

Hassan F Al-Sukhni

An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.

Detecting byte ordering type errors in software code

A processing system includes a processor configured to execute a plurality of instructions corresponding to a task, wherein the plurality of instructions comprises a resource transfer instruction to indicate a transfer of processing operations of the task from the processor to a different resource and a hint instruction which precedes the resource transfer instruction by a set of instructions within the plurality of instructions. A processor task scheduler is configured to schedule tasks to the processor, wherein, in response to execution of the hint instruction of the task, the processor task scheduler finalizes selection of a next task and loads a context of the selected next task into a background register file. The loading occurs concurrently with execution of the set of instructions between the hint instruction and resource transfer instruction, and, after loading is completed, the processor switches to the selected task in response to the resource transfer instruction.

Computer systems and methods with resource transfer hint instruction

A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.

System and method for dynamically managed task switch lookahead

A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Explicit barrier scheduling mechanism for pipelining of stream processing algorithms

A set of instructions executable at an integrated circuit is partitioned into multiple instruction blocks. A first and second instruction block are executed multiple times, including a first execution and a second execution. The first execution of the first instruction block is associated with a first set of executions, and the first execution of the second instruction block is associated with a second set of executions. A first amount of energy consumption representative of a member of the first set of executions is determined, and a second amount of energy consumption representative of a member of the second set of executions is determined. The first amount of energy is assigned to each member of the first set, and the second amount of energy is assigned to each member of the second set, and used to determine a total amount of energy consumption associated with execution of the set of instructions.

Power estimation method and device therefor

Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.

Prefetching using hashed program counter

A first prefetch engine from a first plurality of prefetch engines is allocated to a first load instruction in response to a buffer miss of an iteration of the first load instruction in a program stream. The first plurality of prefetch engines include prefetch engines for prefetching data from memory to a buffer based on a predicted stride. A second prefetch engine from a second plurality of prefetch engines is allocated to the first load instruction in response to the buffer miss. The second plurality of prefetch engines include prefetch engines for prefetching data from memory to the buffer based on an instruction loop representative of a sequence of instructions that affect an address value associated with an allocated load instruction. One of the first or second prefetch engines is deallocated if the other prefetch engine achieves a prefetch performance greater than a first threshold value.

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Austin, TX, United States of America

James C Holt