Bell Telephone Laboratories

At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

James C Candy

Bruce A Wooley

William Herbert Ninke

Yau-Chau Ching

Bernard G King

Stanley Leon Freeny

The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage. Each of the three stages further includes a separate subprocessing means for processing the resultant accumulated digital value from the associated accumulation means at the end of each group period to produce a separated processed digital value which, when combined with the processed digital values from the other stages at the end of a group period, provides a single sinc.sup.3 processed digital value for the N input signal samples of each input group.

Digital-to-digital code converter

Digital signals are processed by a first accumulator to generate most significant bits which represent the signal to be converted but with truncation noise. The error signals from the first accumulator are processed by a second accumulator to generate a second set of most significant bits which are used to remove the truncation noise. The most significant bits from the second accumulator are converted to analog form, differentiated and then combined with the most significant bits from the first accumulator after being converted from digital to analog form. The combined signal is then amplified and filtered.

Higher order interpolation for digital-to-analog conversion

A terrestrial light beam communication system is described for compatible utilization with existing radio transmission systems. The transmitter (FIG. 4) utilizes aiming means (41 and 42) to control the aim of the transmitted light beam. The receiver employs an array of detectors (FIG. 5) from which a circuit (FIG. 6) determines the position of the received light beam. The position of the received light beam is used to control the position of the transmitted light beam from which control signals are developed to maintain the aim of the transmitted light beam to combat the occurrence of ongoing fluctuations in the vertical deflection experienced by the transmitted light beam.

Terrestrial light beam communication system

A digital filter includes a pair of serially connected second order sections (200 and 260), each of which includes delay elements arranged to store the number of bits contained in two complete input words. Each filter section also includes simple logic (220, 230, 270 and 280) comprising adder circuits and inverters but no multipliers. The logic combines outputs from the delay element with the filter input to form an intermediate signal which is applied to the input of the delay element. The intermediate signal is also combined with yet other outputs from the delay element to form the filter output. To eliminate clocking complexity within the filter, the logic is not preset or cleared between each input word. Instead, the word length is intentionally increased, and the sign bit of each intermediate word is intentionally repeated as the word is processed in the filter, the extra bits acting as an inter-word buffer and serving to protect against spurious overflow and limit cycle oscillations.

Logic arrangement for recursive digital filter

An interpolator is arranged to form an increment for each interpolation interval by dividing the difference between the interpolator input and output by a number N indicating the desired number of output samples in the interval. During each interval, the increment is repeatedly added to each output to form the next output.

Linear interpolator

A digital-to-digital converter is arranged to provide 'decimated' output samples at rate f.sub.0, each of which represent a group of input samples received at a rate m times greater. Each output is generated using overlapped triangularly weighted accumulation on an interval including 2m preceding input samples. The samples near the beginning and end of each accumulation interval receive the smallest weight, and the samples at the middle of the interval receive the greatest weight. The converter is achievable in integrated circuit form using first and second serially connected accumulators, the first accumulating m input samples without weighting and the second being used to weight the samples so that the first receives m times the weight of the last sample. The output of the first accumulator is increased in scale by the factor 'm' and the output of the second accumulator subtracted therefrom. The difference is delayed so that the next m samples may be accumulated. The output of the second accumulator is then combined with the delayed subtractor output to yield the desired overlapped, triangularly weighted accumulation.

An analog signal to be converted into a high resolution digital signal is first converted to a coarsely quantized signal by a direct feedback coder. A group of successive coarsely quantized signals are then processed by a converter which produces the high resolution digital signal. In the converter, the processing is performed by an arrangement of two accumulators. The first accumulator provides an output signal indicative of the running sum of each group of coarsely quantized signals. The second accumulator has the capability of providing an accumulation of either the negative or the positive of the output signal of the first accumulator. A negative accumulation is used for a first portion of the group and a positive accumulation is used for the second portion of the group to provide a net sum. The net sum is a triangularly weighted accumulation of the successive signals in the group which occasions self-cancelling of the quantizing noise inherent to the direct feedback coder. Each net sum is used to form a code word of several digital bits in a high accuracy signal. Utilization of a third portion between the first and second portions of the group in which the second accumulator is idle provides a trapezoidal weighting in the net sum. The latter weighting provides a further improvement in resolution and accuracy.

Analog to digital converter with noise suppression

Digital character signals are split into at least two bit groups of different binary significance. The first and most significant of the bit groups is registered and periodically sampled for conversion in a resistor network to an analog format. The bits of the second, or least significant, bit group are utilized to produce a signal train including in a character time a number of pulses determined by the value of the second bit group and which pulses are approximately evenly located in the interval of the character. Each pulse of the train, as it occurs, momentarily augments the most significant bit group. One embodiment is shown in which the signal train produced is successive overflow carries from a high speed accumulation operation initially utilizing the least significant bit group and a starting character and thereafter using the least significant bit group and the immediately preceding accumulation sum. In another embodiment the signal train is produced by a binary rate multiplier, and the least significant bit group is employed to select one of the plural multiplier output frequencies. Embodiments utilizing time compression are also shown.

Digital-to-analog converter with digitally distributed amplitude

In each character time of a pulse code modulation signal stream, the most significant bit group of the PCM character is reversibly incremented and decremented a plurality of times. The incrementing and decrementing is carried out in a selectable sequence for each discrete pair of subintervals in the character time. The selectable sequences are determined by the value of the least significant bit group of the character whereby the average value, over the character time of an analog signal derived from the changing most significant bit group information in each subinterval, is equal to the value represented by the character.

Digital-to-analog decoder utilizing time interpolation and reversible

A shift-companded, or n:m, pulse code, representing on a time-amplitude basis the information of a conventional, amplitude companded, pulse code, is converted to a linear, digital, amplitude, pulse code by first converting the shift-companded amplitude information into 2s-complement form with a number of bits sufficient to yield substantially the same resolution of the encoded information as did the shift-companded code form. Thereafter half of the 2s-complement code words are loaded into an accumulator to be averaged. The resulting digital word representing the average is in 2s-complement, linear PCM format and is thus readily useful for data processing or for further conversion to a commercial, companded, transmission code.

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Tinton Falls, NJ, United States of America

James C Candy