Analog Devices,inc.

James C Camp

Thomas M MacLeod

Carroll Clifton Speir

Ahmed Mohamed Abdelatty Ali

Michael Ray Elliott

Franklin Marshall Murden, Ii

Scott Gregory Bardsley

Ravi Kishore Kummaraguntla

David H Robertson

Bryan Scott Puckett

Joseph Bradford Brannon

Various examples are directed to integrated circuits and/or controllers for battery packs. An integrated circuit for managing at least a portion of a battery pack comprises a first cell controller. The first cell controller may comprise a first switch system, a first local controller, a first receive terminal to receive a first command from a preceding cell controller, and a first transmit terminal to send the first command to a succeeding cell controller. The first switch system may comprise two pairs of switches to couple a first battery cell to a pair of output terminals in an H-bridge configuration. The first local controller may control the first switch system to selectively connect and disconnect the first battery cell to the pair of output terminal.

Battery pack with locally controlled disconnect safeguards

A crest factor reduction (CRF) circuit may include a scaler configured to receive the input signal and generate a scaled input signal. A clipping circuit may be configured to receive the input signal and generate a clipped input signal. A negator circuit may be configured to receive the clipped input signal and generate a negated clipped input signal. A first summer may be configured to sum the scaled input signal and the negated clipped input signal to generate a summed signal. A first digital filter may be configured to receive the summed signal and provide a first digital filter output. A second digital filter may be configured to receive the clipped input signal and provide a second digital filter output. A multiplexer may be configured to receive the first digital filter output and the second digital filter output and generate an output signal.

Crest factor reduction

Embodiments of the present invention are directed to improved battery packaging designs. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions. Moreover, the design may allow for more efficient charging/discharging of the cells that are most ready to accept/supply current.

Battery cell with discretion to drive loads within battery stack

Embodiments of the present invention relate to a battery stack controller system. The system may include a plurality of battery cell stages with cell controller systems (as described above with respect to the first embodiment). The system may also include a stack controller to send charge/discharge commands to the battery stack via a communication network. The stack controller may send the commands to the battery stack based on the requirements of a load or the state of the battery cell stages. The battery cell stages may either comply with the commands or send the commands to neighboring cells via the communication network.

Battery stack with distributed control of cells driving events

Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage.

Battery stack with leapfrogging protocol

Embodiments of the present invention are directed to an improved battery packaging design. The battery pack design may include a battery cell, a plurality of transistors, and a controller. The transistors may be coupled to the terminals of the battery cell in an H-bridge configuration. The controller may control the transistors to bypass the battery cell based on the current flowing between the output terminals of the battery pack. In such a manner, the controller may prevent damage to the battery cell and improve the overall safety of the battery pack in hazardous conditions.

Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.

Variable dynamic range receiver

Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

Pipelined converter systems with enhanced linearity

A communication system includes a multi-channel signal regulation system that limits an aggregate signal in response to an indication that the aggregate signal exceeds a threshold value. The aggregate signal is formed from a combination of the input signals.

Power regulation for a multi-carrier communication system

Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.

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Oak Ridge, NC, United States of America

James C Camp