Motorola Corporation

Tribeam Technologies, Inc.

James C Baker

Henry L Kazecki

John Paul Oliver

Steven H Goode

Michael J Carney

John Jerome Janssen

Donald W Dennis

Kevin Lynn Baum

Bruce D Mueller

Denise Carol Riemer

Brian Keith Classon

Alexander Wayne Hietala

Vipul Anil Desai

Louis Jay Vannatta

Larry C Puhl

Stephen N Levine

David Grant Cason

Christopher P LaRosa

Scott N Carney

Donald L Linder

Christopher P Larosa

Paul S Everline

Charles Choi

Theodore F Longshore

Dale F Bengtson

Nectar Andrew Kirkiris

Daniel M Friend

Steve H Goode

Priya S Nadathur

Kenneth A Renard

Christopher G Rittler

William P DeClerk

William H Balacky

An Infrared Data Association (IrDA) communication range () (e.g., 1 meter) of an IrDA compliant portable device () is increased to an extended range infrared communication (ERIC) range () (e.g., 2 to 40 meters) by extending a transmission range over an uplink channel () from the portable device () up to a base station () and by extending a transmission range over the downlink channel () from the base station () down to the portable device ().

Extended range infrared communication (ERIC) for an infrared associated (IrDA) compliant portable device

Decoding signals represented by a trellis of block length N divided into windows of length L includes a step of decoding a backward recursion from a point P that is after the end of a window back to the end of the window. P is chosen at a sufficient distance from the end of the window such that backward recursion determines a known state metric at the end of the window. A next step includes decoding the window using backward recursion from the known state at the end of the window back to the beginning of the window to define a set of known backward recursion state metrics which are stored. A next step includes decoding using forward recursion starting from a known state at the beginning of the window and moving forward. A next step includes calculating a soft output at each stage of the forward recursion using the stored backward recursion state metrics, and branch metrics at each stage, and outputting the soft output for that stage.

Soft output decoder for convolutional codes

The pulse-shaping look-up table with transient suppression ( ) avoids hard turn-on and turn-off transients by modifying word segments of initial and final digital words during transmission of a digital data sequence. A controller ( ) sends a mode signal and a digital data sequence to the pulse-shaping look-up table with transient suppression ( ). A mode buffer and command block ( ) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block ( ) from the digital data sequence. The digital words are used by a look-up table ( ) to create a sampled digital output waveform sequence. The pulse-shaping look-up table with transient suppression ( ) provides an accurate output waveform sequence with reduced spectral emissions even during start-up and shut-down of digital data transmissions.

Method for suppressing transients using a pulse shaping look-up table

A radio communication device provides extended burst tone detection for a demodulated I and Q input signal. The device includes a first burst detector coupled with the input signal and provides a first detection signal when a FCB tone is detected. A frequency shifter is coupled with the input signal and frequency translates the input signal by a predetermined amount. A second burst detector is coupled with the translated input signal and provides a second detection signal when a FCB tone is detected. A combiner is coupled with the first and second detection signals and indicates FCB tone detection when either of the first and second detection signals indicate FCB tone detection.

Method and apparatus for extended range frequency correction burst detection

A transient-suppressing mode switch ( ) uses a state machine ( ) in conjunction with a soft switch ( ) to control a first mode signal sent from a first mode signal source ( ) to a first soft switch input and a second mode signal from a second mode signal source ( ) to a second soft switch input. When switching from a first mode to a second mode, the state machine delays the transition of the second mode signal from a constant zero value to a non-zero value until after the amplitude of the first mode signal at the first soft switch input has decayed to a sufficiently small value in order to reduce transients caused by switching.

Transient-suppressing mode switch

According to the present disclosure, an parallel formatted data signal is applied to an input (,), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (,) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (,), the delayed second signal is applied to a second parallel-to-serial converter (,), and first and second bit-serial data streams are produced. A controller (,) synchronizes an Arithmetic Logic Unit (,) to the first and second bit-serial data streams so that the ALU (,) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.

Fractional decimator with linear interpolation and method thereof

The pulse-shaping look-up table with transient suppression (530) avoids hard turn-on and turn-off transients by modifying word segments of initial and final digital words during transmission of a digital data sequence. A controller (570) sends a mode signal and a digital data sequence to the pulse-shaping look-up table with transient suppression (530). A mode buffer and command block (560) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block (550) from the digital data sequence. The digital words are used by a look-up table (540) to create a sampled digital output waveform sequence. The pulse-shaping look-up table with transient suppression (530) provides an accurate output waveform sequence with reduced spectral emissions even during start-up and shut-down of digital data transmissions.

Pulse-shaping look-up table with transient suppression

Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Bit-serial linear interpolator with sliced output

According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Method and apparatus for sigma-delta demodulator with aperiodic data

The digital FM receiver back end receives an analog intermediate frequency signal from a radio frequency front end (310) having a heterodyne circuit (312) and an intermediate frequency filter (314). In the receiver back end (307), a digital demodulator (330) having a hard limiter (333), a direct phase digitizer (336), and a phase differential circuit (339) produces a digital phase differential signal from the analog intermediate frequency signal. Next, a digital processor (360) filters and reduces noise in the digital phase differential signal using a bandpass filter (362), a de-emphasis filter (364), and an expandor (366). Finally, a pulse-width-modulation audio amplifier (380) prepares the signal for reproduction on an audio speaker (390). The digital FM receiver back end avoids inherent DC offset problems common to analog FM receivers, and it also offers a reduced complexity, size, and power consumption alternative to conventional digital FM receivers.

Digital FM receiver back end

A bit-serial digital expandor includes a bit-serial dual scaler block (340), a bit-serial rectifier block (320), a bit-serial lowpass wave digital filter block (350), a bit-serial scaler with overflow detection block (360), a bit-serial multiplier block (380), and a bit-serial scaler and clipper block (395). This bit-serial expandor can be used in an AMPS cellular telephone receiver to produce a receiver having a lower silicon area, gate count, and current drain compared to equivalent parallel architecture receivers.

Bit-serial digital expandor

A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

Bit-serial digital compressor

Bit-serial digital filters use numerous flip-flops, which must be reset to a known, all-zero state for testing and start-up purposes. A method for setting a bit-serial digital filter to an all-zero state uses non-resettable flip-flops, which eliminates the increased gate count and current drain overhead of resettable flip-flops. A bit-serial digital filter is constructed using non-resettable flip-flops such as simple non-resettable D flip-flops. When a reset signal is initiated, a reset controller (350) sends an all-zero signal to reset gates (301, 321) positioned at the input to the digital filter and in each feedback loop or unit-delay path. Meanwhile, a bit-serial controller (250) cycles through its control signals to emulate the operation of the bit-serial filter. In two word cycles, each flip-flop in the digital filter will be set to a known, all-zero state, and the all-zero signal is removed to allow normal operation of the filter.

Method and apparatus for setting a bit-serial filter to an all-zero state

In a communications device, two coherent detection algorithms (102 and 103), one of which has a decision feedback equalizer (103), and a detector selection algorithm (104) are used to dynamically select a detector depending on whether delay spread distortion is present. First the correlation of the detector without the equalizer (102) is measured. If this correlation is greater than a predetermined threshold, the data from that detector (102) is used by the communications device. If the correlation is less than the threshold, the correlation of the detector with the equalizer (103) is measured. If this is less than the correlation of the detector without the equalizer (102), the data from the detector without the equalizer (102) is used, otherwise the data is taken from the equalizer (103). In any case, if the detector without the equalizer is used, the detector with the equalizer is turned off.

Method for channel adaptive detecting/equalizing

The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.

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Hanover Park, IL, United States of America

James C Baker