Stmicroelectronics Gmbh

James Brady

Alan H Kramer

James Leon Worley

Duane Giles Laurent

An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively 'shield' the first conductor from some capacitance that the first conductor would normally 'see' without the use of such additional conductors.

Apparatus and method for reducing propagation delay in a conductor system selectable to carry a single signal or independent signals

A row driver circuit receives a supply voltage and operates to develop a boosted voltage having a magnitude that is equal to the sum of an incremental boost voltage and a magnitude of the supply voltage. The magnitude of the incremental boost voltage is a function of the magnitude of the supply voltage to maintain the boosted voltage at an approximately constant value independent of variations in the supply voltage. A method of generating a boosted voltage includes detecting a value of a supply voltage, generating an incremental boost voltage having a value that is a function of the detected supply voltage, and adding the generated incremental boost voltage to the supply voltage to generate the boosted voltage.

Variable boost voltage row driver circuit and method, and memory device and system including same

Apparatus and method for reducing propagation delay in a conductor

A scanning fingerprint detection system includes an array of capacitive sensing elements, the array having a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has first and second conductor plates connected across an inverting amplifier, the conductor plates forming capacitors with the ridges and valleys of a fingerprint of a finger pressed against a protective coating above the array, the inverting amplifier generating a signal indicative of a ridge or valley. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image.

Scanning capacitive semiconductor fingerprint detector

A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

Redundant circuit and method for replacing defective memory cells in a memory device

A scanning fingerprint detection system that includes an array of capacitive sensing elements. The array has a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has a size less than the width of a fingerprint ridge. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image as a fingerprint is moved over the array.

A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first circuit at the one or more predetermined times. A third circuit logically inverts data to be written to and data read from the ferroelectric memory device following every other predetermined time. In this way, the circuit is capable of inverting the data values stored in the ferroelectric memory device, thereby reducing the susceptibility of imprint.

Circuit and method for substantially preventing imprint effects in a ferroelectric memory device

A redundant circuit and method for a semiconductor memory device is disclosed. The redundant circuit includes a programmable circuit for selectively generating at least one first address corresponding to a defective memory row or column line, and shifter circuitry for remapping second addresses which are greater than the first address to row/column lines. For each second address which is greater than the first address, the shifter circuitry remaps the second address to a row/column line which was initially mapped to an immediately higher address relative to the second address. The programmable circuit is capable of generating a plurality of first addresses corresponding to a plurality of defective memory row or column lines.

Memory redundancy device and method

A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

Method and apparatus for testing random access memory devices

A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in which data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell. Testing time for the dynamic memory is thus reduced.

Method and apparatus for testing dynamic random access memory

A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations. Writing a full row of data from the row of latches into a selected row of memory cells includes the steps of disconnecting the row of sense amplifiers from the reference voltage sources; equalizing voltage levels appearing on the bit lines of the semiconductor memory and the sense amplifiers; connecting a row of memory cells to the bit lines; driving at least one bit line of each pair of bit lines to a voltage level representing the data value stored in the corresponding latch; coupling the sense amplifiers to the reference voltage sources for powering the sense amplifiers; and disconnecting the row of memory cells from the bit lines.

Method and apparatus for accessing a memory device

An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.

Apparatus and method for noise reduction in DRAM

A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gate is electrically connected between the first transmission gate and the sense amplifier. A voltage level representing a data bit is loaded directly onto a bit line by turning off the second transmission gate to isolate the sense amplifier from the bit line and turning on the first transmission gate to connect the data line to the bit line. The voltage level on the bit line is then stored in a memory cell connected to the bit line.

Method and apparatus for loading directly onto bit lines in a dynamic

A technique for testing wordline and related circuitry of a memory array is disclosed. The memory array includes a plurality of memory cells arranged in a plurality of rows, wherein each of the plurality of rows has a respective wordline connected to respective ones of the plurality of memory cells. The related circuitry includes a decode circuit connected to each of the respective wordlines for activating at least one of the respective wordlines based upon a corresponding address signal that is decoded by the decode circuit. The technique involves applying an address signal to the decode circuit so as to activate a corresponding one of the respective wordlines, and then monitoring the corresponding one of the respective wordlines so as to determine if the corresponding one of the respective wordlines has been activated and thereby determine if the memory array and related circuitry are operating in a proper manner.

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Plano, TX, United States of America

James Brady