Hewlett-packard Development Company, L.p.

Other

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Computer Computer Corporation

James Benjamin Saxe

David L Detlefs

Charles Gregory Nelson

K Rustan M Leino

David J Sager

Sharad Singhal

Mark David Lillibridge

Raymond Paul Stata

Akhil Sahai

Todd David Millstein

Lyle H Ramshaw

Cormac A Flanagan

To configure a system, models of corresponding components are provided, where the models contain constraints. The models specify that at least one of the components is composed of at least another one of the components. The models are input into a design tool. The design tool generates a configuration of the system that includes the components, wherein the generated configuration satisfies the constraints contained in the models.

Generating a configuration of a system that satisfies constraints contained in models

In a system for statically analyzing a specified computer, a verification condition generator converts the program into a logical equation, called a verification condition, and inserts program flow control labels into the sub-equations of the verification condition. The flow control labels identify conditional branch points in the specified computer program. A theorem prover is applied to the logical equation to determine truth of the logical equation, and when the truth of the logical equation cannot be proved, the theorem prover generates at least one counter-example identifying one of the conditions, one or more variable values inconsistent with that condition, and any of the flow control labels for conditional branch points of the program associated with the identified variable values. A post processing module converts each counter-example into an error message that includes a program trace when the counter-example identifies one or more of the flow control labels.

System and method for verifying computer program correctness and providing recoverable execution trace information

The instructions in a computer program are converted into a form of weakest precondition so as to produce a verification condition that is to be evaluated by a theorem prover. In generating the weakest precondition, labels are introduced for values of variables at control join points. In two preferred embodiments, the computer program is converted into a set of guarded commands prior to the application of weakest precondition operators. In one embodiment, as part of the process of generating the verification condition, assignment commands that assign values to variables are removed from the program through use of a &ldquo;dynamic single assumption&rdquo; technique. In another embodiment, the weakest precondition is expressed in terms of strongest postconditions. In both embodiments, a simplified verification condition is produced in which duplications of sets of instructions following a choice operator is avoided.

Case-reduced verification condition generation system and method using weakest precondition operator expressed using strongest postcondition operators

When a source program containing annotations is processed by a user-selected tool, the annotations in the source program are detected by a lexer and passed to an annotation processor corresponding to the selected tool. The system contains a number of annotation processors and a number of program processing tools, and the annotation processor to which the annotations are passed is selected based upon the user-selected tool. The selected annotation processor converts annotations compatible with the user-selected tool into annotation tokens and returns the annotation tokens to the lexer. The lexer generates tokens based upon the programming-language statements in the source program, and passes both the tokens and annotation tokens to a parser. The parser, in turn, assembles the tokens and annotation tokens into an abstract syntax tree, which is then passed to the user-selected tool for further processing.

System and method for lexing and parsing program annotations

A system and method for increasing the speed of operation of a theorem prover relating to program verification using adaptive pattern matching technique is disclosed. Source code in a specific programming language is converted to one or more formulae, each representing a specific reformulation of the source code that facilitates program verification. Each formula derived from the source code is converted into an E-graph which is a particular type of a directed acyclic graph having leaf nodes and interior nodes. Some of the nodes of an E-graph may be related to other nodes through equivalence relationships. Equivalence relationships between a group of nodes is stored in a data structure called an equivalence class. A collection of rules defining the grammar of the programming language is stored in an axiom database. Rules and conjectures can dynamically be added to the axiom database. Each rule or conjecture to be tested is converted into a pattern. The task of proving a rule or verifying some or all of the source code is transformed to the task of matching a pattern associated with the rule against the nodes of the E-graph. After each round of matching, the E-graph is modified by the addition of new equivalence relationships.

System and method for program verification and optimization

A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Hardware instruction scheduler for short execution unit latencies

A method and apparatus is provided for generating and implementing a 'smooth' schedule for forwarding of cells across a switch in a communication network, such as an AIM network. The schedule is obtained by recursively dividing bandwidth requests into nearly equal subrequests, and selectively allocating the subrequests to slots of a frame in a manner that obtains approximately uniform temporal distribution of cell forwarding over the duration of the frame. Implementation of such a schedule can eliminate clustering of cell forwarding across the switch, thereby reducing latency and space requirements for input and output buffering.

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Palo Alto, CA, United States of America

James Benjamin Saxe