Ati International Srl

Broadcom Corporation

James Battle

Daniel Tai

Haitao Guo

Chad Edward Fogg

John S Thomson

Lordson L Yue

Richard W Webb

Wade K Smith

Chris Goodman

Lakshmi Rao

William N Ng

A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Switch fabric with memory management unit for improved flow control

A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

Optimal initial rasterization starting point

A memory management unit (MMU) for a network switch fabric for forwarding data is disclosed. The MMU has an ingress port interface receiving portions of a data packet and an egress port interface, connected to ingress ports of the fabric through an ingress bus ring. The MMU also includes a cell packer, that groups packet data into cells and a packet pool memory, that stores cells received from the cell packer. The MMU also includes a cell unpacker, where the cell unpacker separates stored cells before releasing the cells to an egress port. The MMU also includes an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules. The priority rules can be a deficit round robin scheduling algorithm or a weighted round robin scheduling algorithm.

Memory management unit architecture for switch fabric

A computer system that performs motion compensation pixels, the computer system includes a storage device; a memory unit that loads at least one error correction value and at least one reference component into the storage device; and a calculation unit coupled to receive the at least one reference component and the at least one error correction value from the storage device. The calculation unit determines multiple predicted components in parallel and stores the multiple predicted components into the storage device. The arrangement, i.e., field or frame type, of the at least one reference component can differ from the arrangement of the stored multiple predicted components.

Motion compensation device

A graphics processing system includes an initial processing system that receives a command to render an image component polygon and generates parameters for calculating image values for the image component polygon. The graphics processing system also includes a backtrack register capable of storing a pixel location. A rasterization engine scans a pixel span in a selected direction and determines whether the pixel span is to be scanned in a direction opposite the selected direction. The rasterization engine stores a backtrack location in the backtrack register in response to a determination that the pixel span is to be scanned in a direction opposite the selected direction, and stores a location to begin scanning a subsequent pixel span in the backtrack register in response to a determination that a backtrack location is not stored in the backtrack register. The rasterization engine also calculates image values for each pixel in the pixel span in the current scan direction. A pixel data processing system receives the image values from the rasterization engine and stores the image values in a frame buffer for display. The graphics processing system has increased image rendering speed without a corresponding increase in the number of logic gates or the amount of chip area required for the rasterization engine.

Method and system for efficient rendering of image component polygons

A novel pipeline processing system includes a parameter bus and a command processor. The command processor receives a command, generates a word in response to the command, and transmits the word on the parameter bus. The word includes information identifying whether the word includes state parameter data and information identifying whether the word includes immediate mode parameter data. A plurality of pipeline stages are positioned along the parameter bus. Each pipeline stage has a state register and a logic block both connected to the parameter bus. The state register receives the word and stores the state parameter data included in the word in response to the information identifying whether the word includes state parameter data. The logic block receives the word and performs a logic operation using state parameter data stored in the state register and the immediate mode parameter data included in the word in response to the information identifying whether the word includes immediate mode parameter data. This pipeline processing system allows state parameter changes to be effected in the pipeline without first draining the pipeline of existing data.

Pipeline processing system and method

A circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results to form a value of higher precision than that yielded by typical circuit implementations for bilinear interpolation operation.

High-precision bilinear interpolation

A method for rendering polygons in a computer graphics system in which the computer display is divided into a plurality of subregions, and the rasterization process is performed in a micro framebuffer for each subregion, rather than sending raster data for each triangle into the frame buffer. Each polygon undergoes a first stage bounding box intersection test to identify the subregions which are likely to intersect with the polygon. If the number or configuration of intersected subregions exceeds a predetermined threshold requirement, then the polygon undergoes a more precise second stage intersection test to identify which subregions are actually intersected by the polygon. If the number or configuration of intersected subregions is below the threshold requirement, then the control data for the polygon is passed on to each of the identified subregions.

Binsorter triangle insertion optimization

A 3-D graphics system combines a software programmed setup processor, a 3-D pipeline, and a software programmed back end processor. The setup processor performs &ldquo;setup&rdquo; on polygons for the 3-D pipeline. The 3-D pipeline rasterizes the polygons to create pixels. The back end processor performs back end processing, such as Z-buffering and alpha blending on the pixels. In one embodiment, the throughput of the 3-D graphics system is increased by clusterizing the pixels before back end processing. Specifically, a clusterizer combines pixels into clusters that can be processed by the back end processors without data coherency problems. Furthermore, the pixels are selected for a cluster to minimize memory latency and access times. In some embodiments, clusters are filled with fill addresses by a cluster filler. The filled addresses generated by the cluster filler, do not cause potential hazards in the back end processor.

Pixel clustering for improved graphics throughput

A prefetch buffer architecture includes a prefetch buffer connected to a memory unit via a global bus. A continue detect unit is also connected to the global bus via a global bus interface. The continue detect unit examines prefetched data words for a predetermined bit pattern indicating the possible presence of a &ldquo;continue&rdquo; command. The continue detect unit may use one or more comparator circuits to compare each prefetched data word with the predetermined bit pattern. Multiple comparator circuits can be used in parallel to simultaneously examine multiple data words. When the continue detect unit determines that a data word contains the predetermined bit pattern, indicating the likely presence of a &ldquo;continue&rdquo; command, the prefetch operation is suspended. The data word likely to contain the &ldquo;continue&rdquo; command is stored in the prefetch buffer until it is called by a decode unit, which decodes the continue command. Once the continue command is decoded, the prefetching operations may resume by prefetching data at the appropriate data address, i.e., the &ldquo;continue&rdquo; address. The continue detect unit may also provide the &ldquo;continue&rdquo; address to a prefetch control unit so that the prefetching operation may be resumed at the proper &ldquo;continue&rdquo; address without waiting for the address to be decoded by the decoding unit.

Growing community of inventors

San Jose, CA, United States of America

James Battle