Hewlett-packard Company

Emulex Design & Manufacturing Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Emulex Corporation

Giganet, Inc.

Apollo Computer Inc.

James B Williams

Shawn Adam Clayton

Maria Clara Gutierrez

Michael L Ziegler

William R Bryg

Nitin Dhiroobhai Godiwala

David R Follett

Kenneth K Chan

Robert D Odineal

Richard F Prohaska

Thomas R Hotchkiss

Harold E Roman

Craig R Frink

Carl John Lindeborg

David James Duckman

James Winston Smart

William Irving Leavitt

Robert J Brooks

John Leland Wood

Alexander Nicolson, Iv

John L Wood

John F Shelton

David S Wells

Bino Joseph Sebastian

Bahman Sharifipour

Ehsan Rashid

Brendan A Voge

Robert E Naas

Shawn A Clayton

A system for enabling input/out virtualization for a device is disclosed. In one embodiment the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Inline PCI-IOV adapter

A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Disclosed herein is an improved method of using sockets in connection with TCP over certain local networks, such as the enhanced Ethernet. In particular, an accelerated socket protocol is provided to enhance data communications between different host computer systems connected to an enhanced Ethernet network. Under the accelerated socket protocol, a host computer, while sending a number of data packets, is able to indicate a particular data packet is a last ready data packet out of all packets ready to be sent by setting a PUSH bit in that particular data packet, which triggers an automatic acknowledgement message that confirms receipt of data from the receiver. In addition, while receiving data packets, the host computer can advertise an effective window that corresponds to the actually available receiving space in the host computer.

Accelerated sockets

An improved method of using sockets in connection with TCP over certain local networks, such as the enhanced Ethernet. In particular, an accelerated socket protocol is provided to enhance data communications between different host computer systems connected to an enhanced Ethernet network. Under the accelerated socket protocol, a host computer, while sending a number of data packets, is able to indicate a particular data packet is a last ready data packet out of all packets ready to be sent by setting a PUSH bit in that particular data packet, which triggers an automatic acknowledgement message that confirms receipt of data from the receiver. In addition, while receiving data packets, the host computer can advertise an effective window that corresponds to the actually available receiving space in the host computer.

The use of Ethernet as an underlying transport for Fiber Channel (FC) frames is disclosed in the Fiber Channel Over Ethernet (FCOE) protocol. In FCOE, the FC physical layer and part of the FC-2 link layer are replaced with the Ethernet physical and link layers. Each FC frame is encapsulated within an Ethernet Frame. The payload of the FCOE frame contains type information from the FC Start Of Frame (SOF) indicator, the FC header, an optional FC payload, and type information from the FC End Of Frame (EOF) indicator. In one embodiment, an Ethernet network carrying FCOE replaces a standard FC network. In another embodiment, devices implementing FCOE may be implemented in a blade server. The entire backplane is Ethernet, over which both storage and networking traffic can be run. The Ethernet links are connected to an Ethernet switch, a FCOE/FC converter, and a FC switch.

Fibre channel over Ethernet

An apparatus and method is disclosed for reducing the computational overhead incurred by a host processor during packet processing and improving network performance by adding additional functionality to a Network Interface Controller (NIC). Under certain circumstances the NIC coalesces multiple receive packets into a single coalesced packet stored within a coalesce buffer in host memory. The coalesced packet includes an Ethernet header, a coalesced Internet Protocol (IP) header, a coalesced Transmission Control Protocol (TCP) header, and a coalesced TCP payload containing the TCP payloads of the multiple receive packets. By coalescing received packets into fewer larger coalesced packets within the host memory, the host software needed to process a receive packet will be invoked less often, meaning that less processor overhead is incurred in the host.

Receive coalescing and automatic acknowledge in network interface controller

Systems and techniques to synchronize network configuration for a hardware accelerated network protocol. According to an aspect, a network configuration record is maintained for a hardware-accelerated network-protocol device, a network configuration store is monitored to identify a network configuration change, and the hardware-accelerated network-protocol device is reconfigured, in response to the identified network configuration change, based on the network configuration record and the network configuration change.

Network configuration synchronization for hardware accelerated network protocol

A method and system comprising a host system and a host bus adapter (HBA). The HBA is configured to handle a Virtual Interface and Transmission Control Protocol (TCP)/Internet Protocol (IP) processing for applications running on the host system.

Virtual interface over a transport protocol

The avoidance of port collisions in a hardware-accelerated network protocol, such as Transmission Control Protocol (TCP)/Internet Protocol (IP), is disclosed. In one example, a hardware-accelerated host bus adaptor (HBA) offloads protocol processing from a host computer's operating system. However, a port collision occurs if a non-accelerated host TCP/IP stack and a hardware accelerated host bus adapter TCP/IP stack choose the same port for establishing a network connection. In a double-ended TCP/IP acceleration connection, a unique TCP port is bound to the accelerated TCP/IP stack. In a single-ended TCP/IP acceleration connection, either the host TCP/IP stack is prevented from using that port or a non-accelerated connection is associated with an accelerated connection without binding a port.

Avoiding port collisions in hardware-accelerated network protocol

A system includes a plurality of computers interconnected by a network including one or more switching nodes. The computers transfer messages over virtual circuits established thereamong. A computer, as a source computer for one or more virtual circuit(s), schedules transmission of messages on a round-robin basis as among the virtual circuits for which it is source computer. Each switching node which forms part of a path for respective virtual circuits also forwards messages for virtual circuits in a round-robin manner, and, a computer, as a destination computer for one or more virtual circuit(s), schedules processing of received messages in a round-robin manner. Round-robin transmission, forwarding and processing at the destination provides a degree of fairness in message transmission as among the virtual circuits established over the network. In addition, messages are transmitted in one or more cells, with the round-robin transmission being on a cell basis, so as to reduce delays which may occur for short messages if a long messages were transmitted in full for one virtual circuit before beginning transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node along the path for the virtual circuit can generate a virtual circuit flow control message for transmission to the source computer to temporarily limit transmission over the virtual circuit if the amount of resources being taken up by messages for the virtual circuit exceeds predetermined thresholds, further providing fairness as among the virtual circuits. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices in the network to temporarily limit transmission thereto if the amount of resources taken up by all virtual circuits exceeds predetermined thresholds, so as to reduce the likelihood of message loss.

System and method for scheduling message transmission and processing in a digital data network

System and method for regulating message flow in a digital data network

A system, method, software and firmware configured to write a message comprising a plurality of words into a memory, such that a last word of the message is written first at a first memory address and a first word of the message is written last at a memory address higher than the first memory address. The system may comprise two software applications sending messages to each other via a bus, such as a PCI bus.

Reverse message writes and reads

A system comprising a host and a network interface card or host bus adapter. The host is configured to perform transport protocol processing. The network interface card is configured to directly place data from a network into a buffer memory in the host.

Direct data placement

A system includes interconnected computers and switching nodes. A source computer for the virtual circuits schedules message transmissions on a round-robin basis. Each switching node also forwards messages in a round-robin manner, and a destination computer schedules processing of received messages in a round-robin manner. In addition, messages are transmitted in cells to reduce delays in short messages if long messages are transmitted for one virtual circuit before transmission of a short message for another virtual circuit. For each virtual circuit, the destination computer and each switching node can generate a virtual circuit flow control message to temporarily limit transmissions if the resources being taken up by messages exceed predetermined thresholds. In addition, each switching node or computer can generate link flow control messages for transmission to neighboring devices to temporarily limit transmissions if the resources taken up by all virtual circuits exceeds predetermined thresholds.

Growing community of inventors

Lowell, MA, United States of America

James B Williams