National Semiconductor Corporation

University of California

James B Wieser

Abhijit M Phanse

Peter J Sallaway

Sreen A Raghavan

Tulsi Manickam

Vijaya G Ceekala

Laurence Douglas Lewicki

Jamal Ramdani

Dennis M Monticelli

Michael X Maida

Lawrence Herbert Zuckerman

Varadarajan Devnath

Luu Thanh Nguyen

Jitendra Mohan

Ramsin Michael Ziazadeh

Kevin E Brehmer

Alan Erik Segervall

Christina P Phan

Matthew James Webb

Duncan James Bremner

Paul Mawson

Devnath Varadarajan

Kenneth D Pedrotti

Randall Walberg

Jacob Adams Wysocki

Suman H Patel

Ray Allen Reed

Robert Dahlgren

Lawrence K Whitcomb

Moulay Mohamed Ibourk

Roger K Benton

Carlos A Laber

A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.

Heart monitoring system or other system for measuring magnetic fields

A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field. The chopping could involve intermittently shielding the magnetic field sensor from the magnetic field or moving the magnetic field sensor with respect to the magnetic field.

Magneto electric sensor with injected up-conversion or down-conversion

A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.

Transceiver system with analog and digital signal echo cancellation having adaptably adjustable filter characteristics

An analog equalizer (and) adaptively equalizes an input analog signal affected with intersymbol interference ('ISI'), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter () converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer () adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder () decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (and) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of one of the equalizers depend adaptively on adaptive adjustments of the filter characteristics of the other equalizer.

Receiver system with interdependent adaptive analog and digital signal equalization

Analog echo-cancelling circuitry (and) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter () converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (and) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder () decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.

Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light.

Molded optical package with fiber coupling feature

A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (y). The pre-filter produces a filtered analog signal (Z) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnction to produce an equalized digital signal (a') as a stream of equalized digital values. Coefficients cand care fixed. Each other coefficient cis adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols. A receiver system may include two or more receivers each configured in the foregoing way with the digital equalization circuitry in each receiver operating according to a transfer function where at least coefficients c, c, and care non-zero.

Receiver system having analog pre-filter and digital equalizer

An analog equalizer (and) adaptively equalizes an input analog signal affected with intersymbol interference ('ISI'), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter () converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer () adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder () decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (and) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of the analog equalizer depend adaptively on adaptive adjustments of the filter characteristics of the digital equalizer.

A skew measurement system and method wherein each of the signals among which the skew is to be determined is connected one at a time to a clock recovery loop. The locked state of the clock recovery loop is used as an indicator of the skew of the data signal relative to the internal clock of the clock recovery loop. By measuring the difference between the locked state of different signals, their relative skew can be measured.

Apparatus and method for skew measurement

A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.

Voltage mode serial interface driver with PVT compensated impedance

A receiver system suitable for a local area network contains an analog pre-filter (or), an analog-to-digital converter (), a digital equalizer (), and a decoder (). A symbol-information-carrying input analog signal (y), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Z) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (bs+1)/(as+as+1) or (1&#x2212;V)+VPF(s) where Vis adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a') as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.

A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.

Differential signal generator with built-in test circuitry

There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.

Receiver architecture using mixed analog and digital signal processing and method of operation

A band-gap reference circuit with averaged current mirror offsets is provided that includes a differential amplifier circuit, a low current transistor circuit, a high current transistor circuit, and a configuration circuit. The differential amplifier circuit includes a first input node operable to receive a first input signal, a second input node operable to receive a second input signal, and an output node operable to generate an output signal based on the input signal difference. The low current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the first input signal based on the output signal. The high current transistor circuit is coupled to the differential amplifier circuit and is operable to receive the output signal and to generate the second input signal based on the output signal. The configuration circuit is coupled to the low current transistor circuit and to the high current transistor circuit. The configuration circuit is operable to configure the band-gap reference circuit for a plurality of states by switching a plurality of components between the low current transistor circuit and the high current transistor circuit at specified intervals.

Growing community of inventors

Pleasanton, CA, United States of America

James B Wieser