Data General Corporation

James B Stein

Robert W Beauchamp

David G Therrien

David L Keating

John J Doyle

Jonathan S Blau

James E Veres

Harold R Kimmens

David W Baird

Richard W Reeves

Michael J Roman

A method and system for handling a branch instruction which requires branching from a current instruction of a first instruction sequence to the first instruction of a second instruction sequence. The branch instruction is fetched and the next instruction of the first sequence is fetched while the branch instruction is displacement formatted. The first instruction of the second sequence is fetched while such next instruction is displacement formatted and the branch instruction is executed. The second instruction of the second sequence is fetched while the first instruction is displacement formatted, but the next instruction of the first sequence is not executed so that an execution wait occurs. The third instruction of the second sequence is then fetched while the second instruction is displacement formatted and the first instruction is executed.

Unconditional wide branch instruction acceleration

A technique for starting up a data processing system in which a 'basic' or 'kernel' instruction set is stored in an auxiliary store and transferred to the processor's control store in start-up. The kernel instruction set in used to execute an initialization program which identifies an I/O device in which a microcode local program and a desired microcode file are stored. No microcode load program is transferred to the processor's main memory, using the kernel instructions and the desired microcode file is then transferred in selected blocks from the I/O device to the main memory and there to the microcode control store. The microinstructions of the desired microcode file then can be used to load appropriate operating system software so that the overall processor is then ready for use in whatever applications are desirable.

Unique process for loading a microcode control store in a data

A data processing system using separate fixed point and floating point computation units and a single control store means for controlling the operations of both units, the units being responsive to commonly shared control fields of the microinstructions supplied from the control store means during their respective operations. The floating point unit can provide single or double precision results, an additional control field of the microinstructions identifying which result is required.

Fixed point and floating point computation units using commonly shared

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Grafton, MA, United States of America

James B Stein