Ag Communication Systems Corporation

James B Southway, Jr

Thomas J Perry

Randall L Brown

James F Hoff

John Wesley Spenik

Frank Sciabica

Kevin B Plyler

Satrio P Mualim

Scott J Baer

Michael Gilbert

Jeffrey Glenn Hunt

A system that provides secure transmission of data between a subscriber's PC and an online service provider (OLS) over an Ethernet WAN. The system includes a remote transceiver unit located at a subscriber site and connected to the subscriber's PC; a central transceiver unit located at a telephone central office and connected to the remote transceiver unit over a twisted pair network and also connected to a WAN; an authorization server that is connected to the WAN; and one or more OLSs, which may include Internet service providers, connected to the WAN. Security of transmission is provided through a method in which only subscriber transmissions directed to a session-specific OLS are allowed to pass through the central transceiver unit onto the WAN, and only unicast transmissions from authorized OLSs are allowed to pass through the central transceiver unit to the subscriber port of the remote transceiver unit. Broadcast transmissions are minimized in favor of unicast messages. The authorization server delivers the IP and MAC addresses of the session-specific OLSs and the subscriber's PC to the remote transceiver units.

Wide area network system providing secure transmission

A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit patterns stored in the interface enable and disable registers, that interface will be enabled or disabled, respectively. The event bus gives the monitor system the ability to simultaneously monitor for multiple bit patterns on the monitored bus, and to monitor for a sequence of bit patterns by having one monitor circuit trigger another.

Bus monitor system

Growing community of inventors

Glendale, AZ, United States of America

James B Southway, Jr