Thinking Machines Corporation

James B Salem

W Daniel Hillis

Guy Lewis Steele, Jr

Brewster A Kahle

Clifford A Lasser

Karl P Sims

Michael Drumbeller

Guy Blelloch

Abhiram Ranade

A method is described for simulating a hexagonal array of computer processors or memories in a computer in which the processor and/or memories are physically connected in a rectilinear grid. The grid provides for communication between adjacent processors in both the horizontal and vertical directions. Thus, it provides physical connections between each processor and four nearest neighbor processors. Each processor is provided with two additional nearest neighbor processors by providing communication between each processor of the array and two additional adjacent processors located on different diagonals in the array. As a result of this arrangement the two additional processors are located either in the same column but in different rows adjacent to the row in which the neighboring processor is located or they are in the same row but in different columns adjacent to the column in which the neighboring processor is located. These additional communication patterns for all the processors add to the rectilinear array a zig zag communication pattern running through the array in either the vertical or horizontal direction.

Method of simulating a hexagonal array of computer processors and/or

A virtual processor mechanism and specific techniques and instructions for utilizing such virtual processor mechanism within an SIMD computer having numerous processors, and each physical processor having dedicated memory associated therewith. Each physical processor is used to simulate multiple 'virtual' processors, with each physical processor simulating the same number of virtual processors. The memory of each physical processor is divided into n regions of equal size, each such region being allocated to one virtual processor, where n is the number of virtual processors simulated by each physical processor. Whenever an instruction is processed, each physical processor is time-sliced among the virtual memory regions, performing the operation first as one virtual processor, then another, until the operation has been performed for all virtual processors. Physical processors are switched among the virtual processors in a completely regular, predictable, deterministic fashion. The virtual processor mechanism switches among virtual processors within instructions, so that at the completion of each instruction, it has been executed on behalf of all virtual processors. A number of instructions are shown for execution using these virtual processor techniques.

Virtual processor techniques in a SIMD multiprocessor array

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James B Salem