Vlsi Technology, Inc.

James B Nolan

Ned D Garinger

William K Hilton

Walter H Potts

Kenneth P Caviasca

Tein-Yow Yu

W Henry Potts

Jeffrey M Michelsen

Pratiksh Parikh

A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This is accomplished by providing first and second alternate RAM sets of 12 registers each, which are accessed in the same 768K to 960K space as the standard twelve registers located in the 768K to 960K space. Access to the 24 registers in the first and second alternate sets of registers is controlled by two control bits. These bits translate address signals directed to the 768K to 960K space to be directed to one or the other of the first and second alternate sets of 12 registers; so that the alternate registers are accessed in the same space as the standard 12 registers in this 768K to 960K space.

Programmable control of EMS page register addresses

Apparatus for digitally trimming the output frequency of a real-time clock is disclosed. The output frequency of a divider chain is adjusted by the contents of a trim constant register. The amount of correction and direction (slow or fast) to be effected is determined by the trim constant register. During 'slow' real-time clock operation, the divider chain 'shortens' the next second produced by the real-time clock. During 'fast' real-time clock operation, the production of the next second is blocked and then a portion of the 'blocked' signal is 'added back' to effectively 'lengthen' the next second produced by the real-time clock.

On-chip frequency trimming method for real-time clock

A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount. A selector, for example, a multiplexor, selects output from either the first frequency divider or the second frequency divider as the system clock signal. When the first oscillating signal is being used to generate the system clock, the second input may be used to control the selection of frequency dividers.

Variable frequency clock for a computer system

A write protection circuit for the Real Time Clock (RTC) Random Access Memory (RAM) of a computer prevents the writing of data into the RTC RAM in the event of a power supply interruption, including write operations which are in progress during removal or interruption of the power supply. This is accomplished by latching both the address and the data in a buffer instead of connecting the respective address and data buses directly to the destination address location in the RTC RAM. In addition, once the data is buffered, the actual write signal to the internal destination of the RTC RAM is delayed until termination of the write strobe pulse. Once the write strobe pulse is terminated; and, additionally, if no power supply interruption has occurred during the latching of the data, an asynchronous monostable multivibrator generates a delayed write strobe which is used to transfer the latched data to the RTC RAM.

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Phoenix, AZ, United States of America

James B Nolan