Advanced Micro Devices Corporation

Apple Inc.

Broadcom Corporation

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Compaq Information Technologies Group, L.p.

P.a. Semi, Inc.

Hewlett-packard Development Company, L.p.

Other

Alpha Processor, Inc.

Api Networks, Inc.

James B Keller

Derrick R Meyer

James Han Wang

Zongjian Chen

Sridhar Subramanian

Rahul Razdan

Ramesh B Gunna

Timothy John Millet

Richard Eugene Kessler

Robert E Stewart

Dale E Gulick

Gerard Richard Williams

Keith R Schakel

Ramsey W Haddad

Mark Douglas Hummel

Manu Gulati

Joseph Byron Rowlands

Wei-Han Lien

Ruchi Wadhawan

Jonathan Mercer Owen

George Kong Yiu

David Arthur James Webb, Jr

Puneet Sharma

Larry David Hewitt

Sukalpa Biswas

Laurent Rene Moll

Stephan G Meier

Mark Hayter

Tse-Yu Yeh

John H Mylius

Francis M Matus

Geoffrey S Strongin

Hao Chen

Gurjeet S Saund

R Stephen Polzin

Po-Yung Chang

Conrado Blasco-Allue

Raj K Ramanujan

Thomas S Green

Luka Bodrozic

Simon C Steely, Jr

David B Witt

Michael G Frank

Patrick Y Law

Stephen R Van Doren

Kevin John McGrath

Brian J Campbell

James Y Cho

Barton Sano

Koray Oner

Chun Hung Ning

David A Webb, Jr

Kwong-Tak Chui

William A Samaras

Jesse Pan

John DeRosa

Solomon J Katzman

Debra Bernstein

William Alexander Hughes

Sandeep Kumar Gupta

Ian D Kountanis

Michael T Clark

Daniel Lawrence Leibholz

Daniel W Dobberpuhl

Suparn Vats

Shyam Sundar

Barry J Flahive

Stephen C Root

Paul Geoffrey Lowney

Paul J Natusch

Steven Ho

Fang Liu

David Howard Asher

Eugene L Yu

Jay C Stickney

David A Webb

Paul J Lemmon

James D Huggins

James J Reisert

Kevin L Ladd

Tse-Yuh Yeh

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Combined transparent/non-transparent cache

A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

Zero cycle move

A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.

Optimizing register initialization operations

A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

Instruction set architecture mode dependent sub-size access of register with associated status indication

Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption.

Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage

In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a 'fetch group'), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, branch prediction values from multiple entries in each table may be read and respective branch prediction values may be combined to form branch predictions for up to M branches in the fetch group.

Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries

In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

Bandwidth management

An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Trust zone support in system on a chip having security enclave processor

One or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, for example. Some systems that include a hierarchical communication fabric may also include fabric control circuits that may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

Fabric limiter circuits

In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

Cache implementing multiple replacement policies

A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting them to the right one contact pad.

Stacked memory device having a scalable bandwidth interface

Growing community of inventors

Redwood City, CA, United States of America

James B Keller