Honeywell G.m.b.h.

Atmel Corporation

Honeywell International Inc.

James B Hobbs

James L Tucker

Kenneth Henry Heffner

Jeffrey P Graebel

Gary Roosevelt

In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.

Integrated circuit stack

A delay element including a stack of p-channel transistors connected in series and a stack of n-channel transistors connected in series with the source of the top p-channel transistor connected to a positive voltage and the source of the bottom n-channel transistor connected to ground. The drain of each n-channel transistor is connected to the drain of a corresponding one of the p-channel transistors and all gates are interconnected and serve as the input to the delay element. The output of the delay element can be any one of the drain connections.

Delay element for integrated circuits

A multiple port memory includes memory cells with merged PNP and NPN bipolar transistors. Each memory cell has a pair of PNP load transistors and a pair of NPN control transistors in a symmetric arrangement. One or more storage ports provides differential signals on two lines which can modify current flow in the memory cell. Similarly, one or more retrieval ports can be connected to two lines connected to the memory cell for reading current flow in the memory cell.

Multiple port memory including merged bipolar transistors

A discharge circuit for memory cell selection interconnection line pairs with the voltage of one pair member sensed by a sensing means with respect to a reference voltage to control the discharge of the other by a controlled current sink means.

Memory current sink

A memory cell circuit with a pair of load bipolar transistors and a pair of control bipolar transistors, and with a pair of supplemental transistors providing current shunts.

Memory cell circuit with supplemental current

The improvement of the present invention provides configurable selection circuitry, which may be used to substitute auxiliary memory locations into a matrix memory. The configurable selection circuitry, after configuration, operates in response to selected signals to drive an auxiliary memory location while disabling the memory location formerly driven by the selected signals.

Configurable memory address decoder for integrated memory circuits with

A memory cell includes two active load, pnp transistors, and two npn switching transistors. The collector and base regions of the switching transistors are cross coupled. Each of the load transistors have two collectors, with the base of each load transistor directly connected to only one of its two collectors. The additional collector prevents the switching transistors from heavily saturating and thus increases the speed of operation of the cell.

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Minneapolis, MN, United States of America

James B Hobbs