Other

Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Bull Nh Information Systems, Inc.

James B Geyer

Victor M Morganti

Thomas C Geyer

Patrick E Prange

George J Barlow

The cycle seat with adjustable sides includes laterally adjustable side wings for increased rider stability. The seat is mounted on arcuately articulating arms that pivot from the lower forward frame of the cycle. The arms are biased upwardly by a spring, thus urging the seat into contact with the rider. A latch mechanism allows the rider to latch the seat position in a lower range for normal riding, or to latch the seat in a higher range to support the rider as he or she stands on the pedals to exert greater force during acceleration or uphill riding. The greater support provided by the raised seat and articulating support mechanism during such riding greatly reduces the amount of upper body exertion the rider would otherwise need to stabilize him or herself using the cycle handlebars, thus freeing the rider to exert greater pedal force during such extreme cycling operations.

Cycle seat with adjustable sides

The cycle seat with adjustable sides includes a base plate having a forward and optionally a rearward guide plate thereon. Each guide plate includes laterally adjustable left and right arm extensions, with each arm having a generally vertical wing extending upwardly therefrom. The arms of each pair simultaneously adjust inwardly and outwardly opposite one another, permitting a single adjustment to adjust both wings of a set equally. Each wing pair includes a latch mechanism, which is adjustable as the cyclist rides the cycle. The seat may be installed per se upon a bicycle or other cycle, or may be installed in combination with a longitudinal and/or arcuate and vertical adjustment mechanism for the seat. The cycle seat greatly reduces or eliminates the need for a pommel, while assuring that the seat remains in contact with the hips and/or thighs of the cyclist at all times to assure more complete control.

A bicycle seat and adjustable mount includes an arcuate rail extending generally upward and backward from a base mounted on a bicycle seat post, and a seat support slidably mounted on the rail and capable of being positioned at various positions along the rail. The seat support preferably carries a seat having a planar laterally elongated base with terminal upstanding hip restraints to position the rider on the seat.

Bicycle seat assembly

In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group. The interprocessor communication has only a minor impact on the performance of the source processor and the target processor because of the command implementation by apparatus.

Apparatus and method for interprocessor communication

In a data processing system, a measurement of the cumulative time used in the performance of an intermittent activity can be required. To determine this cumulative time, a memory location is designated during initialization that is to contain the value of the system clock determined at each initiation of the intermittent activity. A second memory location is provided during initialization that is to contain the accumulated total of the measurements taken to perform the intermittent activity. At each termination of the intermittent activity, the contents of the first and second locations are retrieved from the main memory. The value stored in the first main memory location is then subtracted from the system clock value at the termination of the current intermittent activity and the resulting value is added to the contents of the second location. The resulting value of the addition operation is then stored in the second main memory location. This procedure is implemented with a single instruction and the instruction uses processor working registers for intermediate storage to expedite execution of the instruction.

Single instruction updating of processing time field using software

In a multiprocessor, multiprogrammed data processing system employing virtual addressing, apparatus and method are provided for selecting a page frame in a main memory unit to be replaced by a new page frame of logic signal groups required by a processor. Rather than utilize an algorithm implemented in a series of logical decisions determined by a software procedure, the present invention provides for a single instruction that uses the status signals included with a page descriptor to address an entry in a table of resulting status signals. The relationship between the status signals and the table entries implements the algorithm. The table with entries of resulting status signals is associated with the instruction and is stored in the processor when the instruction is prepared for execution by the processor. The resulting status signals are stored with the page descriptor, replacing the original status signals. The resulting status signals are analyzed by a software procedure, the software procedure implementing the page replacement activity and executing other activity indicated by the resulting status signals.

Apparatus and method for implementation of a page frame replacement

In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

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Phoenix, MD, United States of America

James B Geyer