Intel Corporation

James B Crossland

Shivnandan D Kaushik

Mohan J Kumar

Gilbert A Neiger

Toby Opferman

Anil Aggarwal

Eliezer Weissmann

Baiju V Patel

Ohad Falik

Linda J Rankin

Keshavan K Tiruvallur

David J O'Shea

Jason W Brandt

Per H Hammarlund

Ben-Zion Friedman

Michael Mishaeli

Asit K Mallick

Rajesh S Parthasarathy

Leena K Puthiyedath

Luke Hood

Blaise B Fanning

Dion Rodgers

Bryant E Bigbee

Rajesh M Sankaran

Martin Guy Dixon

Alon Naveh

Ittai Anati

H Peter Anvin

Sridhar Muthrasanallur

Jacob Doweck

Jose Andy Vargas

Chris J Newburn

Don Alan Van Dyke

Andrew V Anderson

Scott Dion Rodgers

Raghunandan Makaram

David A Koufaty

Deborah T Marr

David Lawrence Hill

Beeman C Strong

Theodros Yigzaw

John William Horigan

James S Coke

Benjamin C Chaffin

John L Reid

Shiv Kaushik

Atul A Khare

Jack Doweck

Will Deutsch

Muhammad Faisal Azeem

Altug Koker

Mark Jay Charney

Hong Wang

Andrew F Glew

Francis X Mckeen

Sujoy Sen

Murugasamy K Nachimuthu

Steven M Bennett

Aditya Navale

Koichi Yamada

Boris Ginzburg

Ernie F Brickell

Ilan Pardo

John Thomas Shen

Stephen Anthony Fischer

Devadatta V Bodas

Philip R Lantz

Ashok Raj

Darrell D Boggs

Russell Jerome Fenger

Dean A Mulla

Xiang Chris Zou

Gideon Gerzon

Andrew J Fish

Ashish Gupta

Lily Pao Looi

Xiaoning Li

Doron Orenstein

Suresh K Marisetty

Dave B Minturn

Justin J Song

Shaun M Conrad

John G Holm

Rajesh R Shah

Joseph Frank Cihula

Randolph L Campbell

Gaurav Khanna

Keith Robert Pflederer

Larry O Smith

Ling Cen

Cameron B McNairy

Scott D Brenden

Robert J Kushlis

Rajeev Gopalakrishna

William G Auld

Greg D Cummings

Anthony E Luck

Rahul Seth

Brian L Vajda

Rajesh R Sha

A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

Methods, apparatus, and instructions for user-level thread suspension

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Linear to physical address translation with support for page attributes

Methods, apparatus, and instructions for user level thread suspension

Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Apparatuses and methods for generating a suppressed address trace

A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy, specifically, to replace traditional mass storage that is accessible by an I/O. The computer system includes a processor to execute software and a memory coupled to the processor. At least a portion of the memory comprises a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable by the processor. The system further comprises a memory controller coupled to the NVRAM to perform a memory access operation to access the NVRAM in response to a request from the software for access to a mass storage.

System for configuring partitions within non-volatile random access memory (NVRAM) as a replacement for traditional mass storage

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.

RAM disk using non-volatile random access memory

A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

Instruction and logic for machine checking communication

Apparatus for configuring partitions within phase change memory of tablet computer with integrated memory controller emulating mass storage to storage driver based on request from software

In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

Machine check summary register

An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Systems and methods for preventing unauthorized stack pivoting

Robust system call and system return instructions are executed by a processor to transfer control between a requester and an operating system kernel. The processor includes execution circuitry and registers that store pointers to data structures in memory. The execution circuitry receives a system call instruction from a requester to transfer control from a first privilege level of the requester to a second privilege level of an operating system kernel. In response, the execution circuitry swaps the data structures that are pointed to by the registers between the requester and the operating system kernel in one atomic transition.

Robust and high performance instructions for system call

Growing community of inventors

Banks, OR, United States of America

James B Crossland