National Semiconductor Corporation

The Engineering Consortium, Inc.

Micrel, Incorporated

Etymotic Research, Inc.

Synectics Corporation

James B Compton

Clyde M Brown, Jr

Martin J Alter

Daniel D Culmer

Sam S Ochi

Robert A Cometta

Mead C Killion

Jonathan K Stewart

Donald L Wilson

Steven J Iseberg

Norman P Matzen

Clyde &ldquo;Kip&rdquo; M Brown, Jr

Stephen L Daleo

Clyde Kip M Brown, Jr

William A Cole

Clyde 'Kip Brown, Jr

A compact polarity-insensitive integrated circuit amplifier is described designed to be powered by a miniature low voltage battery of variable polarity. Low current, polarity corrected voltage sources are integrated into functional blocks to supply low current non-bidirectional elements and to provide a constant polarity bias to a substrate of CMOS circuits. Polarity corrected voltage sources are used to provide a polarity sensing function. The invention is embodied in a Class D amplifier which may comprise four n-channel MOSFET transistors arranged in an H-bridge configuration. Additional driver circuitry is described which increases the voltage of the pulse-width modulated input signal to the MOSFET transistors and also performs a pulse trimming function, which reduces parasitic crowbar currents in the amplifier output stage.

Battery polarity insensitive integrated circuit amplifier

A battery polarity insensitive amplifier utilizes a power management architecture to reduce the size of the circuitry used to accomplish the polarity correction function. An efficient Class D amplifier and compact voltage multiplying driver circuit reduce the size of the battery polarity insensitive amplifier circuit.

A high fidelity hearing aid amplifier is operable at a very low battery voltage and includes a single integrated circuit chip which provides a variable gain amplifier and gain control circuitry operative at low signal levels to enhance gain at higher frequencies relative to gain at lower frequencies, such circuitry including a logarithmic rectifier arrangement and a peak detector in a compression ratio control circuit. Operation at a low battery voltage is enhanced through a compression ratio control circuit which provides a level shift between an AC output of the logarithmic rectifier arrangement and the peak detector. Current mirrors are provided to obtained balanced and stable operation, and an arrangement is provided for manual control by a user to obtain an optimum response characteristic.

High fidelity hearing aid amplifier

A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A substantially square contact opening is made to expose the P-type region and a portion of the N-type region. Sides of the contact opening are formed to be at substantially 45 degree angles with respect to sides of the substantially square P-type region. In this manner, the alignment tolerance for forming the contact opening is less critical than if the sides of the contact opening were parallel to the sides of the P-type region. The contact opening is then filled with a conductive material to electrically short the P-type region to the N-type region. The conductivity types in this example may be reversed.

Method for forming shorting contact for semiconductor which allows for

A diamond-shaped short contact overlapping two differing conductivity regions in a semiconductor. The shape and orientation providing maximum alignment tolerances for a given size of contact opening.

Diamond shorting contact for semiconductors

A monolithic switching array integrated with control logic on a dielectrically isolated monolithic substrate is provided wherein individual components are constructed in abutment with the oxide walls of the dielectrically isolated wells to form a diffusion/wall interface. As a consequence, area of the wells can be optimally used, and undesired electric fields around the components are minimized, thus allowing for smaller overall chip dimensions as compared with comparable prior art dielectric isolation (d.i.) or junction isolated construction techniques. Moreover, d.i. construction eliminates undesired parasitic devices in a monolithic circuit and allows for improved system accuracy.

Solid state monolithic switching device

An element of an integrated circuit, such as an ion implanted region or a metal layer, may be laser trimmed without exposing P-N junctions or other circuit elements not to be trimmed to damage by the laser through use of the present protection process and structure. In the process, an oxide through which the laser trimming is carried out is formed over a selected portion of the circuit to be trimmed by the laser. A bare layer of a metal reflective to the laser radiant energy beam, such as aluminum, gold or silver, is formed surrounding the selected portion of the circuit. The selected portion of the integrated circuit is then trimmed with the laser. The oxide promotes trimming in the selected area by absorbing the laser radiant energy beam. The bare metal layer protects the portion of the integrated circuit underlying it by reflecting most of its energy.

Laser trim protection process and structure

Laser trim protection process

A junction field effect transistor is incorporated into a conventional monolithic bipolar integrated circuit using compatible processing steps. The transistor source and drain regions are produced during IC base diffusion and the gate contact during IC emitter diffusion. A channel is ion implanted in the region between source and drain. A second, shallower, opposite conductivity ion implant is applied over the channel so as to overlap and cover. Thus, a subsurface channel is created. A third ion implant of slightly deeper character and to a much heavier dosage is created in the region between and separated from the source and drain using an impurity of the same conductivity type as the second ion implant. This third ion implant is designed to span the channel without contacting either the source or drain, thus creating a top gate ohmically connected to the bottom gate.

Junction field effect transistor for use in integrated circuits

In an integrated circuit structure a subsurface isolation layer is doped by diffusion during wafer processing. A substrate is first doped by ion implantation to create surface layer of the opposite conductivity type. Where substrate connections are to be created a heavier deposit of dopant is established using an impurity that will confer conductivity of the same polarity as the substrate. The wafer is then overgrown with an intrinsic layer that will be subsequently doped by diffusion of the ion implanted dopant. Then conventional integrated circuit processing is employed using buried conductive layers, epitaxy, isolation and device diffusion. The transistors thus produced can be designed to have isolation or substrate connected collectors as determined by the substrate surface doping.

Method for making integrated circuit transistors with isolation and

A pair of FET's are coupled in series between the emitter and collector of a bipolar transistor and the juncture of the FET's coupled to the bipolar transistor base. The FET gates are coupled to the bipolar transistor collector. When a current is passed through the emitter-collector terminals in excess of a threshold value, a constant voltage will appear over a substantial current range. The constant voltage is related to FET Vp and can be used to compensate or track integrated circuits that contain both FET's and bipolar transistors.

Circuit combining bipolar transistor and JFET's to produce a constant

A field effect transistor (FET) is designed to act as an off-on type switch by the control of a driver voltage applied to its gate electrode. A driver circuit, responsive to a toggling current, provides a control of gate electrode voltage. The circuit includes means for rapidly switching the FET on and off while drawing relatively low current in the off and on states. Improvements relate to means for speeding up turn on time and reducing charge transferred to the circuit being switched by the FET.

Field effect transistor switch

A novel FET switching circuit including a high beta transistor in an analog switch FET circuit for rapid, low power consumption with transient current pull up to the FET switching circuit to the on condition. A novel circuit is utilized and coupled to the transistor for the derivation of a reference voltage for the turn off of the analog switch FET. A novel transistor - JFET nonsaturating switching circuit which gives high speed turn off is incorporated.

Growing community of inventors

Los Gatos, CA, United States of America

James B Compton