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Trw Limited

James B Cho

George W McIver

John R Marum

A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.

Triple redundant fault-tolerant register

An adjunct switch circuit is provided for detecting power to ground leaks in a portion of a chip circuit and for disabling such circuit portion in the event of a leak. The switch circuit of the invention is particularly useful for Wafer Scale Integration, and is conveniently employed in the testing of chip circuits following manufacturing. In a preferred embodiment, the switch circuit includes a power supply, including a voltage source and a ground, a reset line for receiving a reset pulse, a first switch, connected in series with one of the power supply lines to the circuit portion ground and inversely responsive to both the reset pulse and the state of the circuit portion ground following termination of the reset pulse, and a second switch, connected between ground and the circuit portion ground and directly responsive to the reset pulse to leak current from the circuit portion ground to ground when turned on by the reset pulse.

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Gardena, CA, United States of America

James B Cho