National Semiconductor Corporation

Elantec, Inc.

James B Cecil

William H Gross

Joseph J Connolly, Jr

Robert C Dobkin

Thomas M Frederiksen

James E Solomon

An integrated circuit voltage regulator employs a PNP pass transistor to produce a low dropout voltage. Saturation in the pass transistor produces excessive substrate current which appears in the form of wasted current which lowers the regulator efficiency. A current conducted by the sat catcher circuit is employed to avoid pass transistor saturation. The sat catcher is controlled dynamically so the dropout voltage is minimized and the voltage regulator maintains good performance at high regulator output currents.

Circuit to reduce dropout voltage in a low dropout voltage regulator

A logic-controlled circuit superimposes a constant voltage across an actuator or motor load that is driven by a bridge-type amplifier to control the constant velocity operation of such load in response to an applied logic signal that may also disable the bridge-type amplifier.

Resistor programmable velocity controller

An overload protection circuit for a disableable amplifier includes a sensing resistor connected to provide indication of the current supplied to the amplifier and includes logic circuitry for producing a disabling control signal for a selected time interval following detection of the overload condition of the amplifier.

Digital protection circuit and method for linear amplifier

A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

Multi stage resistive ladder network having extra stages for trimming

The disclosed digital to analog conversion circuit is comprised of a plurality of resistors interconnected as an N stage R-2R ladder network, a pair of conductive buses, and a total of N transistorized switches which respectively couple the output legs of the ladder to a selectable one of the buses in response to digital logic signals. Those switches which couple to the legs of the K most significant stages have scaled resistances that differ by powers of two; whereas the remaining switches have resistances which equal the largest scaled resistance. An MOS transistor lies in the serial leg of the Kth stage. This transistor has a resistance of approximately 2/3 the largest scaled resistance of the switches. The unscaled resistances provide for ease of fabrication, while the MOS transistor improves the accuracy with which digital to analog conversions are performed.

Digital to analog conversion circuit including compensation FET'S

A statistically enhanced ratio-matched network in a circuit chip is disclosed. The network may be either a resistance network or a capacitance network. In a ratio-matched resistance network, such as an R-2R resistance ladder, a plurality of resistances in a circuit chip have a rational ratio of resistance values to each other. All of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions, and certain critical resistances each consists of a series-parallel combination of the resistors for statistically enhancing the accuracy of the rational ratio of the critical resistances to each other.

Statistical enhancement of the accuracy of a ratio-matched network in a

A digital-to-analog converter having a nonlinear transfer characteristic includes a voltage divider connected in parallel with a reference voltage and a switching array connected to the voltage divider. The switching array is actuated in accordance with the digital word which is being converted to an analog signal. The voltage divider is dimensioned to provide a nonlinear transfer characteristic. The digital-to-analog circuit is also employed for performing a successive approximation analog-to-digital conversion. The voltage divider is an integrated circuit resistor formed of an elongated strip of one polarity diffused in a semiconductor substrate of the opposite polarity, and some of the switches of the array are integrated circuit switches in which a portion of the continuous strip forms one terminal thereof.

Conversion circuit

The invention described herein is an interface circuit which effectively allows TTL output voltages to fall within the range of CMOS input thresholds. The interface circuit contains bipolar and FET devices connected to generate an input voltage threshold which is equal to two base-emitter voltage drops. The interface circuit also includes a switching circuit portion which comprises one P-channel MOS transistor connected to one N-channel MOS transistor.

Growing community of inventors

Santa Clara, CA, United States of America

James B Cecil